97 lines
3.2 KiB
Systemverilog
97 lines
3.2 KiB
Systemverilog
/*****************************************************************************\
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| Copyright (C) 2021-2025 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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// Macros for building Hazard3 with RVFI trace port outside of the
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// riscv-formal test harness. For example, when including the trace port in a
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// synthesised processor.
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`ifdef HAZARD3_RVFI_STANDALONE
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`define RISCV_FORMAL
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`define RISCV_FORMAL_NRET 1
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`define RISCV_FORMAL_XLEN 32
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`define RISCV_FORMAL_ILEN 32
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`define RISCV_FORMAL_MEM_FAULT
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`define RISCV_FORMAL_ALIGNED_MEM
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`define RVFI_OUTPUTS \
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output wire rvfi_valid, \
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output wire [63:0] rvfi_order, \
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output wire [31:0] rvfi_insn, \
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output wire rvfi_trap, \
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output wire rvfi_halt, \
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output wire rvfi_intr, \
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output wire [1:0] rvfi_mode, \
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output wire [1:0] rvfi_ixl, \
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output wire [4:0] rvfi_rs1_addr, \
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output wire [4:0] rvfi_rs2_addr, \
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output wire [31:0] rvfi_rs1_rdata, \
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output wire [31:0] rvfi_rs2_rdata, \
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output wire [4:0] rvfi_rd_addr, \
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output wire [31:0] rvfi_rd_wdata, \
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output wire [31:0] rvfi_pc_rdata, \
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output wire [31:0] rvfi_pc_wdata, \
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output wire [31:0] rvfi_mem_addr, \
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output wire [3:0] rvfi_mem_rmask, \
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output wire [3:0] rvfi_mem_wmask, \
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output wire [31:0] rvfi_mem_rdata, \
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output wire [31:0] rvfi_mem_wdata, \
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output wire rvfi_mem_fault, \
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output wire [3:0] rvfi_mem_fault_rmask, \
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output wire [3:0] rvfi_mem_fault_wmask
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`define RVFI_WIRES \
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wire rvfi_valid; \
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wire [63:0] rvfi_order; \
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wire [31:0] rvfi_insn; \
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wire rvfi_trap; \
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wire rvfi_halt; \
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wire rvfi_intr; \
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wire [1:0] rvfi_mode; \
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wire [1:0] rvfi_ixl; \
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wire [4:0] rvfi_rs1_addr; \
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wire [4:0] rvfi_rs2_addr; \
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wire [31:0] rvfi_rs1_rdata; \
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wire [31:0] rvfi_rs2_rdata; \
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wire [4:0] rvfi_rd_addr; \
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wire [31:0] rvfi_rd_wdata; \
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wire [31:0] rvfi_pc_rdata; \
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wire [31:0] rvfi_pc_wdata; \
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wire [31:0] rvfi_mem_addr; \
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wire [3:0] rvfi_mem_rmask; \
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wire [3:0] rvfi_mem_wmask; \
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wire [31:0] rvfi_mem_rdata; \
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wire [31:0] rvfi_mem_wdata; \
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wire rvfi_mem_fault; \
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wire [3:0] rvfi_mem_fault_rmask; \
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wire [3:0] rvfi_mem_fault_wmask;
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`define RVFI_CONN \
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.rvfi_valid (rvfi_valid), \
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.rvfi_order (rvfi_order), \
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.rvfi_insn (rvfi_insn), \
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.rvfi_trap (rvfi_trap), \
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.rvfi_halt (rvfi_halt), \
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.rvfi_intr (rvfi_intr), \
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.rvfi_mode (rvfi_mode), \
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.rvfi_ixl (rvfi_ixl), \
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.rvfi_rs1_addr (rvfi_rs1_addr), \
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.rvfi_rs2_addr (rvfi_rs2_addr), \
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.rvfi_rs1_rdata (rvfi_rs1_rdata), \
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.rvfi_rs2_rdata (rvfi_rs2_rdata), \
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.rvfi_rd_addr (rvfi_rd_addr), \
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.rvfi_rd_wdata (rvfi_rd_wdata), \
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.rvfi_pc_rdata (rvfi_pc_rdata), \
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.rvfi_pc_wdata (rvfi_pc_wdata), \
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.rvfi_mem_addr (rvfi_mem_addr), \
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.rvfi_mem_rmask (rvfi_mem_rmask), \
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.rvfi_mem_wmask (rvfi_mem_wmask), \
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.rvfi_mem_rdata (rvfi_mem_rdata), \
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.rvfi_mem_wdata (rvfi_mem_wdata), \
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.rvfi_mem_fault (rvfi_mem_fault), \
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.rvfi_mem_fault_rmask (rvfi_mem_fault_rmask), \
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.rvfi_mem_fault_wmask (rvfi_mem_fault_wmask)
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`endif
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