907 lines
35 KiB
Verilog
907 lines
35 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2021-2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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`default_nettype none
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module hazard3_frontend #(
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`include "hazard3_config.vh"
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) (
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input wire clk,
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input wire rst_n,
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// Fetch interface
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// addr_vld may be asserted at any time, but after assertion,
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// neither addr nor addr_vld may change until the cycle after addr_rdy.
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// There is no backpressure on the data interface; the front end
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// must ensure it does not request data it cannot receive.
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// addr_rdy and dat_vld may be functions of hready, and
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// may not be used to compute combinational outputs.
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output wire mem_size, // 1'b1 -> 32 bit access
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output wire [W_ADDR-1:0] mem_addr,
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output wire mem_priv,
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output wire mem_addr_vld,
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input wire mem_addr_rdy,
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input wire [W_DATA-1:0] mem_data,
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input wire mem_data_err,
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input wire mem_data_vld,
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// Jump/flush interface
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// Processor may assert vld at any time. The request will not go through
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// unless rdy is high. Processor *may* alter request during this time.
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// Inputs must not be a function of hready.
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input wire [W_ADDR-1:0] jump_target,
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input wire jump_priv,
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input wire jump_target_vld,
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output wire jump_target_rdy,
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// Interface to the branch target buffer. `src_addr` is the address of the
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// last halfword of a taken backward branch. The frontend redirects fetch
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// such that `src_addr` appears to be sequentially followed by `target`.
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input wire btb_set,
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input wire [W_ADDR-1:0] btb_set_src_addr,
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input wire btb_set_src_size,
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input wire [W_ADDR-1:0] btb_set_target_addr,
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input wire btb_clear,
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output wire [W_ADDR-1:0] btb_target_addr_out,
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// Interface to Decode
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output reg [31:0] cir, // Current instruction register; pre-expanded to 32-bit
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output wire [31:0] cir_raw, // Unexpanded instruction data
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output reg [1:0] cir_vld, // number of valid halfwords in CIR
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input wire [1:0] cir_use, // number of halfwords D intends to consume
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// *may* be a function of hready
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output wire [1:0] cir_err, // Bus error on upper/lower halfword of CIR.
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output wire [1:0] cir_predbranch, // Set for last halfword of a predicted-taken branch
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output wire cir_break_any, // Set for exact match of a breakpoint address on CIR LSB
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output wire cir_break_d_mode, // As above but specifically break to debug mode
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output reg cir_is_32bit, // Can't be decoded from CIR due to pre-expansion
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output reg cir_invalid_16bit, // Expanded an invalid 32-bit instruction
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output reg cir_is_uop, // Current instruction is part of a micro-op sequence
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output reg cir_uop_nonfinal, // ...and there are more to follow in this instruction
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output reg cir_uop_no_pc_update, // Suppress PC increment or jump (note the jump in cm.popret is not the final uop!)
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output reg cir_uop_atomic, // Prevent IRQ entry, so intermediate states are not observed
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input wire uop_stall,
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input wire uop_clear,
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// "flush_behind": do not flush the oldest instruction when accepting a
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// jump request (but still flush younger instructions). Sometimes a
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// stalled instruction may assert a jump request, because e.g. the stall
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// is dependent on a bus stall signal so can't gate the request.
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input wire cir_flush_behind,
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// Required for regnum predecode when Zilsd is enabled:
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input wire df_lspair_phase_next,
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// Signal to power controller that power down is safe. (When going to
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// sleep, first the pipeline is stalled, and then the power controller
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// waits for the frontend to naturally come to a halt before releasing
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// its power request. This avoids manually halting the frontend.)
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output wire pwrdown_ok,
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// Signal to delay the first instruction fetch following reset, because
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// powerup has not yet been negotiated.
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input wire delay_first_fetch,
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// Provide the rs1/rs2 register numbers which will be in CIR next cycle.
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// Coarse: valid if this instruction has a nonzero register operand.
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// (Suitable for regfile read)
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output reg [4:0] predecode_rs1_coarse,
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output reg [4:0] predecode_rs2_coarse,
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// Fine: like coarse, but accurate zeroing when the operand is implicit.
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// (Suitable for bypass. Still not precise enough for stall logic.)
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output reg [4:0] predecode_rs1_fine,
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output reg [4:0] predecode_rs2_fine,
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// Debugger instruction injection: instruction fetch is suppressed when in
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// debug halt state, and the DM can then inject instructions into the last
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// entry of the prefetch queue using the vld/rdy handshake.
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input wire debug_mode,
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input wire [W_DATA-1:0] dbg_instr_data,
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input wire dbg_instr_data_vld,
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output wire dbg_instr_data_rdy,
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// PMP query->kill interface for X permission checks
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output wire [W_ADDR-1:0] pmp_i_addr,
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output wire pmp_i_m_mode,
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input wire pmp_i_kill,
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// Trigger unit query->break interface for breakpoints
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output wire [W_ADDR-1:0] trigger_addr,
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output wire trigger_m_mode,
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input wire [1:0] trigger_break_any,
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input wire [1:0] trigger_break_d_mode
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);
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`include "rv_opcodes.vh"
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localparam W_BUNDLE = 16;
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// This is the minimum for full throughput (enough to avoid dropping data when
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// decode stalls) and there is no significant advantage to going larger.
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localparam FIFO_DEPTH = 2;
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// ----------------------------------------------------------------------------
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// Fetch queue
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wire jump_now = jump_target_vld && jump_target_rdy;
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reg [1:0] mem_data_hwvld;
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// PMP X faults are checked in parallel with the fetch (fine if executable
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// memory is read-idempotent) and failures are promoted to bus errors:
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wire pmp_kill_fetch_dph;
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wire mem_or_pmp_err = mem_data_err || pmp_kill_fetch_dph;
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// Similarly, breakpoint matches are checked during fetch data phase. These
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// are called mem_xxx because they are the breakpoint metadata for the data
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// coming back from memory in this dphase.
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wire [1:0] mem_break_any;
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wire [1:0] mem_break_d_mode;
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// Mark data as containing a predicted-taken branch instruction so that
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// mispredicts can be recovered -- need to track both halfwords so that we
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// can mark the entire instruction, and nothing but the instruction:
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reg [1:0] mem_data_predbranch;
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// Bus errors (and other metadata) travel alongside data. They cause an
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// exception if the core decodes the instruction, but until then can be
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// flushed harmlessly.
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reg [W_DATA-1:0] fifo_mem [0:FIFO_DEPTH];
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reg fifo_err [0:FIFO_DEPTH];
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reg [1:0] fifo_break_any [0:FIFO_DEPTH];
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reg [1:0] fifo_break_d_mode [0:FIFO_DEPTH];
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reg [1:0] fifo_predbranch [0:FIFO_DEPTH];
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reg [1:0] fifo_valid_hw [0:FIFO_DEPTH];
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reg fifo_valid [0:FIFO_DEPTH];
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reg fifo_valid_m1 [0:FIFO_DEPTH];
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wire [W_DATA-1:0] fifo_rdata = fifo_mem[0];
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wire fifo_full = fifo_valid[FIFO_DEPTH - 1];
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wire fifo_empty = !fifo_valid[0];
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wire fifo_almost_full = fifo_valid[FIFO_DEPTH - 2];
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wire fifo_push;
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wire fifo_pop;
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wire fifo_dbg_inject = DEBUG_SUPPORT && dbg_instr_data_vld && dbg_instr_data_rdy;
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always @ (*) begin: boundary_conditions
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integer i;
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fifo_mem[FIFO_DEPTH] = mem_data;
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fifo_predbranch[FIFO_DEPTH] = 2'b00;
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fifo_err[FIFO_DEPTH] = 1'b0;
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fifo_break_any[FIFO_DEPTH] = 2'b00;
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fifo_break_d_mode[FIFO_DEPTH] = 2'b00;
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for (i = 0; i <= FIFO_DEPTH; i = i + 1) begin
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fifo_valid[i] = |EXTENSION_C ? |fifo_valid_hw[i] : fifo_valid_hw[i][0];
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// valid-to-right condition: i == 0 || fifo_valid[i - 1], but without
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// using negative array bound (seems broken in Yosys?) or OOB in the
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// short circuit case (gives lint although result is well-defined)
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if (i == 0) begin
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fifo_valid_m1[i] = 1'b1;
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end else begin
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fifo_valid_m1[i] = fifo_valid[i - 1];
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end
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end
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end
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always @ (posedge clk or negedge rst_n) begin: fifo_update
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integer i;
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if (!rst_n) begin
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for (i = 0; i < FIFO_DEPTH; i = i + 1) begin
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fifo_valid_hw[i] <= 2'b00;
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fifo_mem[i] <= 32'd0;
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fifo_err[i] <= 1'b0;
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fifo_break_any[i] <= 2'b00;
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fifo_break_d_mode[i] <= 2'b00;
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fifo_predbranch[i] <= 2'b00;
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end
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// This exists only for loop boundary conditions, but is tied off in
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// this synchronous process to work around a Verilator scheduling
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// issue (see issue #21)
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fifo_valid_hw[FIFO_DEPTH] <= 2'b00;
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end else begin
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for (i = 0; i < FIFO_DEPTH; i = i + 1) begin
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if (fifo_pop || (fifo_push && !fifo_valid[i])) begin
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fifo_mem[i] <= fifo_valid[i + 1] ? fifo_mem[i + 1] : mem_data;
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fifo_err[i] <= fifo_valid[i + 1] ? fifo_err[i + 1] : mem_or_pmp_err;
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fifo_break_any[i] <= fifo_valid[i + 1] ? fifo_break_any[i + 1] : mem_break_any;
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fifo_break_d_mode[i] <= fifo_valid[i + 1] ? fifo_break_d_mode[i + 1] : mem_break_d_mode;
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fifo_predbranch[i] <= fifo_valid[i + 1] ? fifo_predbranch[i + 1] : mem_data_predbranch;
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end
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fifo_valid_hw[i] <=
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jump_now ? 2'h0 :
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fifo_valid[i + 1] && fifo_pop ? fifo_valid_hw[i + 1] :
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fifo_valid[i] && fifo_pop ? mem_data_hwvld & {2{fifo_push}} :
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fifo_valid[i] ? fifo_valid_hw[i] :
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fifo_push && !fifo_pop && fifo_valid_m1[i] ? mem_data_hwvld : 2'h0;
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end
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// Allow DM to inject instructions directly into the lowest-numbered
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// queue entry. This mux should not extend critical path since it is
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// balanced with the instruction-assembly muxes on the queue bypass
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// path. Note that flush takes precedence over debug injection
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// (and the debug module design must account for this)
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if (fifo_dbg_inject) begin
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fifo_mem[0] <= dbg_instr_data;
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fifo_err[0] <= 1'b0;
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fifo_predbranch[0] <= 2'b00;
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fifo_break_any[0] <= 2'b00;
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fifo_break_d_mode[0] <= 2'b00;
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fifo_valid_hw[0] <= jump_now ? 2'b00 : 2'b11;
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end
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fifo_valid_hw[FIFO_DEPTH] <= 2'b00;
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end
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end
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`ifdef HAZARD3_ASSERTIONS
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always @ (posedge clk) if (rst_n) begin
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// FIFO validity must be compact, so we can always consume from the end
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if (!fifo_valid[0]) begin
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assert(!fifo_valid[1]);
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end
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end
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`endif
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assign pwrdown_ok = (fifo_full && !jump_target_vld) || debug_mode;
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// ----------------------------------------------------------------------------
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// Branch target buffer
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wire [W_ADDR-1:0] btb_src_addr;
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wire btb_src_size;
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wire [W_ADDR-1:0] btb_target_addr;
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wire btb_valid;
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generate
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if (BRANCH_PREDICTOR) begin: have_btb
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reg [W_ADDR-1:0] btb_src_addr_r;
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reg btb_src_size_r;
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reg [W_ADDR-1:0] btb_target_addr_r;
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reg btb_valid_r;
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assign btb_src_addr = btb_src_addr_r;
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assign btb_src_size = btb_src_size_r;
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assign btb_target_addr = btb_target_addr_r;
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assign btb_valid = btb_valid_r;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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btb_src_addr_r <= {W_ADDR{1'b0}};
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btb_src_size_r <= 1'b0;
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btb_target_addr_r <= {W_ADDR{1'b0}};
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btb_valid_r <= 1'b0;
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end else if (btb_clear) begin
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// Clear takes precedences over set. E.g. if a taken branch is in
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// stage 2 and an exception is in stage 3, we must clear the BTB.
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btb_valid_r <= 1'b0;
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end else if (btb_set) begin
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btb_src_addr_r <= btb_set_src_addr;
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btb_src_size_r <= btb_set_src_size;
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btb_target_addr_r <= btb_set_target_addr;
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btb_valid_r <= 1'b1;
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end
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end
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end else begin: no_btb
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assign btb_src_addr = {W_ADDR{1'b0}};
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assign btb_src_size = 1'b0;
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assign btb_target_addr = {W_ADDR{1'b0}};
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assign btb_valid = 1'b0;
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end
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endgenerate
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// Decode uses the target address to set the PC to the correct branch target
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// value following a predicted-taken branch (as normally it would update PC
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// by following an X jump request, and in this case there is none).
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//
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// Note this assumes the BTB target has not changed by the time the predicted
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// branch arrives at decode! This is always true because the only way for the
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// target address to change is when an older branch is taken, which would
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// flush the younger predicted-taken branch before it reaches decode.
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assign btb_target_addr_out = btb_target_addr;
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// ----------------------------------------------------------------------------
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// Fetch request generation
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// Fetch addr runs ahead of the PC, in word increments.
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reg [W_ADDR-1:0] fetch_addr;
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reg fetch_priv;
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reg btb_prev_start_of_overhanging;
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reg [1:0] mem_aph_hwvld;
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reg mem_addr_hold;
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wire btb_match_word = |BRANCH_PREDICTOR && btb_valid && (
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fetch_addr[W_ADDR-1:2] == btb_src_addr[W_ADDR-1:2]
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);
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// Catch case where predicted-taken branch instruction extends into next word:
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wire btb_src_overhanging = btb_src_size && btb_src_addr[1];
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// Suppress case where we have jumped immediately after a word-aligned halfword-sized
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// branch, and the jump target went into fetch_addr due to an address-phase hold:
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wire btb_jumped_beyond = !btb_src_size && !btb_src_addr[1] && !mem_aph_hwvld[0];
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wire btb_match_current_addr = btb_match_word && !btb_src_overhanging && !btb_jumped_beyond;
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wire btb_match_next_addr = btb_match_word && btb_src_overhanging;
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wire btb_match_now = btb_match_current_addr || btb_prev_start_of_overhanging;
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// Post-increment if jump request is going straight through
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wire [W_ADDR-1:0] jump_target_post_increment =
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{jump_target[W_ADDR-1:2], 2'b00} +
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{{W_ADDR-3{1'b0}}, mem_addr_rdy && !mem_addr_hold, 2'b00};
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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fetch_addr <= RESET_VECTOR;
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// M-mode at reset:
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fetch_priv <= 1'b1;
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btb_prev_start_of_overhanging <= 1'b0;
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end else begin
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if (jump_now) begin
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fetch_addr <= jump_target_post_increment;
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fetch_priv <= jump_priv || !U_MODE;
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btb_prev_start_of_overhanging <= 1'b0;
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end else if (mem_addr_vld && mem_addr_rdy) begin
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if (btb_match_now && |BRANCH_PREDICTOR) begin
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fetch_addr <= {btb_target_addr[W_ADDR-1:2], 2'b00};
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end else begin
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fetch_addr <= fetch_addr + 32'd4;
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end
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btb_prev_start_of_overhanging <= btb_match_next_addr;
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end
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end
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end
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// Combinatorially generate the address-phase request
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reg reset_holdoff;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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reset_holdoff <= 1'b1;
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end else begin
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reset_holdoff <= (|EXTENSION_XH3POWER && delay_first_fetch) ? reset_holdoff : 1'b0;
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// This should be impossible, but assert to be sure, because it *will*
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// change the fetch address (and we shouldn't check it in hardware if
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// we can prove it doesn't happen)
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end
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end
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`ifdef HAZARD3_ASSERTIONS
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always @ (posedge clk) if (rst_n) begin
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assert(!(jump_target_vld && reset_holdoff));
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end
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`endif
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reg [W_ADDR-1:0] mem_addr_r;
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reg mem_priv_r;
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reg mem_addr_vld_r;
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// Downstream accesses are always word-sized word-aligned.
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assign mem_addr = mem_addr_r;
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assign mem_priv = mem_priv_r;
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assign mem_addr_vld = mem_addr_vld_r && !reset_holdoff;
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assign mem_size = 1'b1;
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wire fetch_stall;
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always @ (*) begin
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mem_addr_r = fetch_addr;
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mem_priv_r = fetch_priv;
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mem_addr_vld_r = 1'b1;
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case (1'b1)
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mem_addr_hold : begin mem_addr_r = fetch_addr; end
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jump_target_vld || reset_holdoff : begin
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mem_addr_r = {jump_target[W_ADDR-1:2], 2'b00};
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mem_priv_r = jump_priv || !U_MODE;
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end
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DEBUG_SUPPORT && debug_mode : begin mem_addr_vld_r = 1'b0; end
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!fetch_stall : begin mem_addr_r = fetch_addr; end
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default : begin mem_addr_vld_r = 1'b0; end
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endcase
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end
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assign jump_target_rdy = !mem_addr_hold;
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// ----------------------------------------------------------------------------
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// Bus Pipeline Tracking
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// Keep track of some useful state of the memory interface
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reg [1:0] pending_fetches;
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reg [1:0] ctr_flush_pending;
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wire [1:0] pending_fetches_next = pending_fetches + (mem_addr_vld && !mem_addr_hold) - mem_data_vld;
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// Using the non-registered version of pending_fetches would improve FIFO
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// utilisation, but create a combinatorial path from hready to address phase!
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// This means at least a 2-word FIFO is required for full fetch throughput.
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assign fetch_stall = fifo_full
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|| fifo_almost_full && |pending_fetches
|
|
|| pending_fetches > 2'h1;
|
|
|
|
// Debugger only injects instructions when the frontend is at rest and empty.
|
|
assign dbg_instr_data_rdy = DEBUG_SUPPORT && !fifo_valid[0] && ~|ctr_flush_pending;
|
|
|
|
wire cir_room_for_fetch;
|
|
// If fetch data is forwarded past the FIFO, ensure it is not also written to it.
|
|
assign fifo_push = mem_data_vld && ~|ctr_flush_pending && !(cir_room_for_fetch && fifo_empty)
|
|
&& !(DEBUG_SUPPORT && debug_mode);
|
|
|
|
always @ (posedge clk or negedge rst_n) begin
|
|
if (!rst_n) begin
|
|
mem_addr_hold <= 1'b0;
|
|
pending_fetches <= 2'h0;
|
|
ctr_flush_pending <= 2'h0;
|
|
end else begin
|
|
mem_addr_hold <= mem_addr_vld && !mem_addr_rdy;
|
|
pending_fetches <= pending_fetches_next;
|
|
if (jump_now) begin
|
|
ctr_flush_pending <= pending_fetches - mem_data_vld;
|
|
end else if (|ctr_flush_pending && mem_data_vld) begin
|
|
ctr_flush_pending <= ctr_flush_pending - 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
`ifdef HAZARD3_ASSERTIONS
|
|
always @ (posedge clk) if (rst_n) begin
|
|
assert(ctr_flush_pending <= pending_fetches);
|
|
assert(pending_fetches < 2'd3);
|
|
assert(!(mem_data_vld && !pending_fetches));
|
|
end
|
|
`endif
|
|
|
|
always @ (posedge clk or negedge rst_n) begin
|
|
if (!rst_n) begin
|
|
mem_data_hwvld <= 2'b11;
|
|
mem_aph_hwvld <= 2'b11;
|
|
mem_data_predbranch <= 2'b00;
|
|
end else begin
|
|
if (jump_now) begin
|
|
if (|EXTENSION_C) begin
|
|
if (mem_addr_rdy) begin
|
|
mem_aph_hwvld <= 2'b11;
|
|
mem_data_hwvld <= {1'b1, !jump_target[1]};
|
|
end else begin
|
|
mem_aph_hwvld <= {1'b1, !jump_target[1]};
|
|
end
|
|
end
|
|
mem_data_predbranch <= 2'b00;
|
|
end else if (mem_addr_vld && mem_addr_rdy) begin
|
|
if (|EXTENSION_C) begin
|
|
// If a predicted-taken branch instruction only spans the first
|
|
// half of a word, need to flag the second half as invalid.
|
|
mem_data_hwvld <= mem_aph_hwvld & {
|
|
!(|BRANCH_PREDICTOR && btb_match_now && (btb_src_addr[1] == btb_src_size)),
|
|
1'b1
|
|
};
|
|
// Also need to take the alignment of the destination into account.
|
|
mem_aph_hwvld <= {
|
|
1'b1,
|
|
!(|BRANCH_PREDICTOR && btb_match_now && btb_target_addr[1])
|
|
};
|
|
end
|
|
mem_data_predbranch <=
|
|
|BRANCH_PREDICTOR && btb_match_word ? (
|
|
btb_src_addr[1] ? 2'b10 :
|
|
btb_src_size ? 2'b11 : 2'b01
|
|
) :
|
|
|BRANCH_PREDICTOR && btb_prev_start_of_overhanging ? (
|
|
2'b01
|
|
) : 2'b00;
|
|
end
|
|
end
|
|
end
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// PMP and trigger unit interfacing: query -> kill/break
|
|
|
|
wire [W_ADDR-1:0] pmp_trigger_check_dph_addr;
|
|
wire pmp_trigger_check_dph_m_mode;
|
|
|
|
// Register the fetch address into stage F so that the PMP can check it in
|
|
// parallel with the bus data phase. Feels wasteful to have a separate
|
|
// register, but using the fetch_addr counter is fraught due to the way that
|
|
// new addresses go into it or past it (depending on aphase hold).
|
|
|
|
generate
|
|
if (PMP_REGIONS > 0 || DEBUG_SUPPORT != 0) begin: have_check_reg
|
|
|
|
reg [W_ADDR-1:0] check_addr_dph;
|
|
reg check_m_mode_dph;
|
|
always @ (posedge clk or negedge rst_n) begin
|
|
if (!rst_n) begin
|
|
check_addr_dph <= {W_ADDR{1'b0}};
|
|
check_m_mode_dph <= 1'b0;
|
|
end else if (mem_addr_vld && mem_addr_rdy) begin
|
|
check_addr_dph <= mem_addr;
|
|
check_m_mode_dph <= mem_priv;
|
|
end
|
|
end
|
|
|
|
assign pmp_trigger_check_dph_addr = check_addr_dph;
|
|
assign pmp_trigger_check_dph_m_mode = check_m_mode_dph;
|
|
|
|
end else begin: no_check_reg
|
|
|
|
assign pmp_trigger_check_dph_addr = {W_ADDR{1'b0}};
|
|
assign pmp_trigger_check_dph_m_mode = 1'b0;
|
|
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (PMP_REGIONS == 0) begin: no_pmp
|
|
|
|
assign pmp_i_addr = {W_ADDR{1'b0}};
|
|
assign pmp_i_m_mode = 1'b0;
|
|
assign pmp_kill_fetch_dph = 1'b0;
|
|
|
|
end else begin: have_pmp
|
|
|
|
assign pmp_i_addr = pmp_trigger_check_dph_addr;
|
|
assign pmp_i_m_mode = pmp_trigger_check_dph_m_mode;
|
|
assign pmp_kill_fetch_dph = pmp_i_kill && !debug_mode;
|
|
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (DEBUG_SUPPORT == 0) begin: no_triggers
|
|
|
|
assign trigger_addr = {W_ADDR{1'b0}};
|
|
assign trigger_m_mode = 1'b0;
|
|
assign mem_break_any = 2'b00;
|
|
assign mem_break_d_mode = 2'b00;
|
|
|
|
end else begin: have_triggers
|
|
|
|
assign trigger_addr = pmp_trigger_check_dph_addr;
|
|
assign trigger_m_mode = pmp_trigger_check_dph_m_mode;
|
|
assign mem_break_any = trigger_break_any & {|EXTENSION_C, 1'b1};
|
|
assign mem_break_d_mode = trigger_break_d_mode & {|EXTENSION_C, 1'b1};
|
|
|
|
end
|
|
endgenerate
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Instruction buffer
|
|
|
|
// The instruction buffer is a 3 x ~16-bit shift register:
|
|
//
|
|
// * 2 x 16-bit entries form the 32-bit current instruction register (CIR)
|
|
// which is the processor's decode window
|
|
//
|
|
// * 1 x 16-bit entry allows the decode window to be non-32-bit-aligned with
|
|
// respect to the 2 x 32-bit prefetch queue entries, which are always
|
|
// naturally aligned in memory (if fully populated).
|
|
//
|
|
// The third entry should be trimmed for non-RVC configurations due to
|
|
// constant-folding on EXTENSION_C; it is unnecessary here because the
|
|
// instructions are always 32-bit-aligned.
|
|
|
|
// The entries ("slots") are slightly larger than 16 bits because they also
|
|
// contain metadata like bus errors:
|
|
localparam W_SLOT = 4 + W_BUNDLE;
|
|
localparam SLOT_BREAK_ANY_BIT = 3 + W_BUNDLE;
|
|
localparam SLOT_BREAK_D_MODE_BIT = 2 + W_BUNDLE;
|
|
localparam SLOT_ERR_BIT = 1 + W_BUNDLE;
|
|
localparam SLOT_PREDBRANCH_BIT = 0 + W_BUNDLE;
|
|
|
|
reg [3*W_SLOT-1:0] buf_contents;
|
|
reg [1:0] buf_level;
|
|
|
|
wire fetch_data_vld = !fifo_empty || (mem_data_vld && ~|ctr_flush_pending && !debug_mode);
|
|
|
|
wire [W_DATA-1:0] fetch_data = fifo_empty ? mem_data : fifo_rdata;
|
|
wire [1:0] fetch_data_hwvld = fifo_empty ? mem_data_hwvld : fifo_valid_hw[0];
|
|
wire fetch_bus_err = fifo_empty ? mem_or_pmp_err : fifo_err[0];
|
|
wire [1:0] fetch_break_any = fifo_empty ? mem_break_any : fifo_break_any[0];
|
|
wire [1:0] fetch_break_d_mode = fifo_empty ? mem_break_d_mode : fifo_break_d_mode[0];
|
|
wire [1:0] fetch_predbranch = fifo_empty ? mem_data_predbranch : fifo_predbranch[0];
|
|
|
|
wire [W_SLOT-1:0] fetch_contents_hw1 = {
|
|
fetch_break_any[1],
|
|
fetch_break_d_mode[1],
|
|
fetch_bus_err,
|
|
fetch_predbranch[1],
|
|
fetch_data[W_BUNDLE +: W_BUNDLE]
|
|
};
|
|
|
|
wire [W_SLOT-1:0] fetch_contents_hw0 = {
|
|
fetch_break_any[0],
|
|
fetch_break_d_mode[0],
|
|
fetch_bus_err,
|
|
fetch_predbranch[0],
|
|
fetch_data[0 +: W_BUNDLE]
|
|
};
|
|
|
|
wire [2*W_SLOT-1:0] fetch_contents_aligned = {
|
|
fetch_contents_hw1,
|
|
fetch_data_hwvld[0] || ~|EXTENSION_C ? fetch_contents_hw0 : fetch_contents_hw1
|
|
};
|
|
|
|
// Shift not-yet-used contents down to backfill D's consumption. We don't care
|
|
// about anything which is invalid or will be overlaid with fresh data, so
|
|
// choose these values in a way that minimises muxes.
|
|
wire [3*W_SLOT-1:0] buf_shifted =
|
|
cir_use[1] ? {buf_contents[W_SLOT +: 2 * W_SLOT], buf_contents[2 * W_SLOT +: W_SLOT]} :
|
|
cir_use[0] && EXTENSION_C ? {buf_contents[2 * W_SLOT +: W_SLOT], buf_contents[W_SLOT +: 2 * W_SLOT]} :
|
|
buf_contents;
|
|
|
|
wire [1:0] level_next_no_fetch = buf_level - cir_use;
|
|
|
|
// Overlay fresh fetch data onto the shifted/recycled buffer contents. Again,
|
|
// if something won't be looked at, generate the cheapest possible garbage.
|
|
assign cir_room_for_fetch = level_next_no_fetch <= (|EXTENSION_C && ~&fetch_data_hwvld ? 2'h2 : 2'h1);
|
|
assign fifo_pop = cir_room_for_fetch && !fifo_empty;
|
|
|
|
wire [3*W_SLOT-1:0] buf_shifted_plus_fetch =
|
|
!cir_room_for_fetch ? buf_shifted :
|
|
level_next_no_fetch[1] && |EXTENSION_C ? {fetch_contents_aligned[0 +: W_SLOT], buf_shifted[0 +: 2 * W_SLOT]} :
|
|
level_next_no_fetch[0] && |EXTENSION_C ? {fetch_contents_aligned, buf_shifted[0 +: W_SLOT]} :
|
|
{buf_shifted[2 * W_SLOT +: W_SLOT], fetch_contents_aligned};
|
|
|
|
wire [1:0] fetch_fill_amount = cir_room_for_fetch && fetch_data_vld ? (
|
|
&fetch_data_hwvld || ~|EXTENSION_C ? 2'h2 : 2'h1
|
|
) : 2'h0;
|
|
|
|
wire [1:0] buf_level_next = {1'b1, |EXTENSION_C} & (
|
|
jump_now && cir_flush_behind ? (cir_is_32bit ? 2'h2 : 2'h1) :
|
|
jump_now ? 2'h0 : level_next_no_fetch + fetch_fill_amount
|
|
);
|
|
|
|
always @ (posedge clk or negedge rst_n) begin
|
|
if (!rst_n) begin
|
|
buf_level <= 2'h0;
|
|
cir_vld <= 2'h0;
|
|
// Mysterious reset value ensures address buses are zero in reset
|
|
// (see definition of d_addr_offs in hazard3_decode)
|
|
buf_contents <= {{3 * W_SLOT - 2{1'b0}}, 2'b11};
|
|
end else begin
|
|
buf_level <= buf_level_next;
|
|
cir_vld <= buf_level_next & ~(buf_level_next >> 1'b1);
|
|
buf_contents <= buf_shifted_plus_fetch;
|
|
end
|
|
end
|
|
|
|
`ifdef HAZARD3_ASSERTIONS
|
|
reg [1:0] prop_past_buf_level; // Workaround for weird non-constant $past reset issue
|
|
always @ (posedge clk) begin
|
|
if (!rst_n) begin
|
|
prop_past_buf_level <= 2'h0;
|
|
end else begin
|
|
prop_past_buf_level <= buf_level;
|
|
|
|
assert(cir_vld <= 2);
|
|
assert(cir_use <= cir_vld);
|
|
if (!jump_now) assert(buf_level_next >= level_next_no_fetch);
|
|
// We fetch 32 bits per cycle, max. If this happens it's due to negative overflow.
|
|
if (prop_past_buf_level == 2'h0)
|
|
assert(buf_level != 2'h3);
|
|
end
|
|
end
|
|
`endif
|
|
|
|
assign cir_err = {
|
|
buf_contents[1 * W_SLOT + SLOT_ERR_BIT],
|
|
buf_contents[0 * W_SLOT + SLOT_ERR_BIT]
|
|
};
|
|
|
|
assign cir_predbranch = {
|
|
buf_contents[1 * W_SLOT + SLOT_PREDBRANCH_BIT],
|
|
buf_contents[0 * W_SLOT + SLOT_PREDBRANCH_BIT]
|
|
};
|
|
|
|
assign cir_break_any = buf_contents[0 * W_SLOT + SLOT_BREAK_ANY_BIT] && |cir_vld;
|
|
|
|
assign cir_break_d_mode = buf_contents[0 * W_SLOT + SLOT_BREAK_D_MODE_BIT] && |cir_vld;
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Register number predecode
|
|
|
|
wire [31:0] next_instr = {
|
|
buf_shifted_plus_fetch[1 * W_SLOT +: W_BUNDLE],
|
|
buf_shifted_plus_fetch[0 * W_SLOT +: W_BUNDLE]
|
|
};
|
|
|
|
wire next_instr_is_32bit = next_instr[1:0] == 2'b11 || ~|EXTENSION_C;
|
|
|
|
wire [3:0] decomp_uop_step;
|
|
wire [3:0] uop_ctr = decomp_uop_step & {4{|EXTENSION_ZCMP}};
|
|
|
|
wire [4:0] zcmp_pushpop_rs2 =
|
|
uop_ctr == 4'h0 ? 5'd01 : // ra
|
|
uop_ctr == 4'h1 ? 5'd08 : // s0
|
|
uop_ctr == 4'h2 ? 5'd09 : // s1
|
|
5'd15 + {1'b0, uop_ctr} ; // s2-s11
|
|
|
|
wire [4:0] zcmp_pushpop_rs1 =
|
|
uop_ctr < 4'hd ? 5'd02 : // sp (addr base reg)
|
|
uop_ctr == 4'hd ? 5'd00 : // zero (clear a0)
|
|
uop_ctr == 4'he ? 5'd01 : // ra (ret)
|
|
5'd02 ; // sp (stack adj)
|
|
|
|
wire [4:0] zcmp_sa01_r1s = {|next_instr[9:8], ~|next_instr[9:8], next_instr[9:7]};
|
|
wire [4:0] zcmp_sa01_r2s = {|next_instr[4:3], ~|next_instr[4:3], next_instr[4:2]};
|
|
|
|
wire [4:0] zcmp_mvsa01_rs1 = {4'h5, uop_ctr[0]};
|
|
wire [4:0] zcmp_mva01s_rs1 = uop_ctr[0] ? zcmp_sa01_r2s : zcmp_sa01_r1s;
|
|
|
|
// "coarse" because the mapping of pair (x0, x1) -> (x0, x0) is not yet applied
|
|
wire [4:0] zilsd_rs2_coarse = { next_instr[24:21], df_lspair_phase_next ^ ~next_instr[15]};
|
|
wire [4:0] zclsd_sd_rs2_coarse = {2'b01, next_instr[4:3], df_lspair_phase_next ^ ~next_instr[7] };
|
|
wire [4:0] zclsd_sdsp_rs2_coarse = { next_instr[6:3], df_lspair_phase_next ^ 1'b1 };
|
|
|
|
always @ (*) begin
|
|
|
|
casez ({next_instr_is_32bit, |EXTENSION_ZCMP, next_instr[15:0]})
|
|
{1'b1, 1'bz, 16'bzzzzzzzzzzzzzzzz}: predecode_rs1_coarse = next_instr[19:15]; // 32-bit R, S, B formats
|
|
{1'b0, 1'bz, 16'b00zzzzzzzzzzzz00}: predecode_rs1_coarse = 5'd2; // c.addi4spn + don't care
|
|
{1'b0, 1'bz, 16'b0zzzzzzzzzzzzz01}: predecode_rs1_coarse = next_instr[11:7]; // c.addi, c.addi16sp + don't care (jal, li)
|
|
{1'b0, 1'bz, 16'bz1zzzzzzzzzzzz10}: predecode_rs1_coarse = 5'd2; // c.lwsp, c.swsp, c.ldsp, c.sdsp
|
|
{1'b0, 1'bz, 16'bz00zzzzzzzzzzz10}: predecode_rs1_coarse = next_instr[11:7]; // c.slli, c.mv, c.add
|
|
{1'b0, 1'b1, 16'b1011zzzzzzzzzz10}: predecode_rs1_coarse = zcmp_pushpop_rs1; // cm.push, cm.pop*
|
|
{1'b0, 1'b1, 16'b1010zzzzz0zzzz10}: predecode_rs1_coarse = zcmp_mvsa01_rs1; // cm.mvsa01
|
|
{1'b0, 1'b1, 16'b1010zzzzz1zzzz10}: predecode_rs1_coarse = zcmp_mva01s_rs1; // cm.mva01s
|
|
default: predecode_rs1_coarse = {2'b01, next_instr[9:7]};
|
|
endcase
|
|
|
|
casez ({next_instr_is_32bit, |EXTENSION_ZCMP, |EXTENSION_ZILSD, |EXTENSION_ZCLSD, next_instr[15:0]})
|
|
{1'b1, 1'bz, 1'b1, 1'bz, 16'bzz11zzzzz0z0zzzz}: predecode_rs2_coarse = zilsd_rs2_coarse; // ld, sd (Zilsd)
|
|
{1'b1, 1'bz, 1'b0, 1'bz, 16'bzz11zzzzz0z0zzzz}: predecode_rs2_coarse = next_instr[24:20]; // ld, sd (no Zilsd)
|
|
|
|
{1'b1, 1'bz, 1'bz, 1'bz, 16'bzz0zzzzzzzzzzzzz}: predecode_rs2_coarse = next_instr[24:20]; // (cover remaining 32-bit
|
|
{1'b1, 1'bz, 1'bz, 1'bz, 16'bzz10zzzzzzzzzzzz}: predecode_rs2_coarse = next_instr[24:20]; // patterns, without overlap)
|
|
{1'b1, 1'bz, 1'bz, 1'bz, 16'bzz11zzzzz1zzzzzz}: predecode_rs2_coarse = next_instr[24:20];
|
|
{1'b1, 1'bz, 1'bz, 1'bz, 16'bzz11zzzzz0z1zzzz}: predecode_rs2_coarse = next_instr[24:20];
|
|
|
|
{1'b0, 1'bz, 1'b1, 1'b1, 16'bzz1zzzzzzzzzzz00}: predecode_rs2_coarse = zclsd_sd_rs2_coarse;
|
|
{1'b0, 1'bz, 1'bz, 1'bz, 16'bzz0zzzzzzzzzzz10}: predecode_rs2_coarse = next_instr[6:2]; // c.add, c.swsp
|
|
{1'b0, 1'b1, 1'bz, 1'bz, 16'bz01zzzzzzzzzzz10}: predecode_rs2_coarse = zcmp_pushpop_rs2; // cm.push
|
|
{1'b0, 1'bz, 1'b1, 1'b1, 16'bz11zzzzzzzzzzz10}: predecode_rs2_coarse = zclsd_sdsp_rs2_coarse;
|
|
default: predecode_rs2_coarse = {2'b01, next_instr[4:2]};
|
|
endcase
|
|
|
|
// The "fine" predecode targets those instructions which either:
|
|
// - Have an implicit zero-register operand in their expanded form (e.g. c.beqz)
|
|
// - Do not have a register operand on that port, but rely on the port being 0
|
|
// We don't care about instructions which ignore the reg ports, e.g. ebreak
|
|
|
|
casez ({|EXTENSION_C, next_instr})
|
|
// -> addi rd, x0, imm:
|
|
{1'b1, 16'hzzzz, `RVOPC_C_LI}: predecode_rs1_fine = 5'd0;
|
|
{1'b1, 16'hzzzz, `RVOPC_C_MV}: begin
|
|
if (next_instr[6:2] == 5'd0) begin
|
|
// c.jr has rs1 as normal
|
|
predecode_rs1_fine = predecode_rs1_coarse;
|
|
end else begin
|
|
// -> add rd, x0, rs2:
|
|
predecode_rs1_fine = 5'd0;
|
|
end
|
|
end
|
|
default: predecode_rs1_fine = predecode_rs1_coarse;
|
|
endcase
|
|
|
|
casez ({|EXTENSION_C, |EXTENSION_ZILSD, |EXTENSION_ZCLSD, next_instr})
|
|
{1'b1, 1'bz, 1'bz, 16'hzzzz, `RVOPC_C_BEQZ}: predecode_rs2_fine = 5'd0; // -> beq rs1, x0, label
|
|
{1'b1, 1'bz, 1'bz, 16'hzzzz, `RVOPC_C_BNEZ}: predecode_rs2_fine = 5'd0; // -> bne rs1, x0, label
|
|
{1'b1, 1'b1, 1'bz, `RVOPC_SD }: predecode_rs2_fine = predecode_rs2_coarse & {5{|next_instr[24:21]}};
|
|
{1'b1, 1'b1, 1'b1, 16'hzzzz, `RVOPC_C_SDSP}: predecode_rs2_fine = predecode_rs2_coarse & {5{|next_instr[ 6: 3]}};
|
|
default: predecode_rs2_fine = predecode_rs2_coarse;
|
|
endcase
|
|
|
|
if (|EXTENSION_E) begin
|
|
predecode_rs1_coarse[4] = 1'b0;
|
|
predecode_rs2_coarse[4] = 1'b0;
|
|
predecode_rs1_fine[4] = 1'b0;
|
|
predecode_rs2_fine[4] = 1'b0;
|
|
end
|
|
|
|
end
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Instruction decompression
|
|
|
|
// Instructions are decompressed at the end of stage 1 (fetch data phase). On
|
|
// ASIC, where the register file is synthesised with muxes, this puts
|
|
// decompression somewhat in parallel with register file read, which uses
|
|
// approximately decoded regnums.
|
|
|
|
generate
|
|
if (~|EXTENSION_C) begin: no_decompress
|
|
|
|
// No decompression; instructions decoded directly from prefetch buffer
|
|
always @ (*) begin
|
|
cir = {
|
|
buf_contents[1 * W_SLOT +: W_BUNDLE],
|
|
buf_contents[0 * W_SLOT +: W_BUNDLE]
|
|
} | 32'd3;
|
|
cir_is_32bit = 1'b1;
|
|
cir_invalid_16bit = ~&buf_contents[1:0];
|
|
cir_is_uop = 1'b0;
|
|
cir_uop_nonfinal = 1'b0;
|
|
cir_uop_no_pc_update = 1'b0;
|
|
cir_uop_atomic = 1'b0;
|
|
end
|
|
|
|
assign decomp_uop_step = 4'h0;
|
|
|
|
end else begin: have_decompress
|
|
|
|
wire decomp_instr_is_32bit;
|
|
wire [31:0] decomp_instr_out;
|
|
wire decomp_is_uop;
|
|
wire decomp_is_final_uop;
|
|
wire decomp_uop_no_pc_update;
|
|
wire decomp_uop_atomic;
|
|
wire decomp_invalid;
|
|
|
|
wire first_uop = ~|decomp_uop_step;
|
|
// Ensure the first uop goes straight through, as it is registered into CIR:
|
|
wire uop_stall_non_first = first_uop ? ~|buf_level_next : uop_stall;
|
|
// Ensure the uop counter stops at 0 after rolling over once:
|
|
wire uop_stall_on_repeat = cir_is_uop && !cir_uop_nonfinal && ~|cir_use;
|
|
|
|
hazard3_instr_decompress #(
|
|
`include "hazard3_config_inst.vh"
|
|
) decomp (
|
|
.clk (clk),
|
|
.rst_n (rst_n),
|
|
|
|
.instr_in (next_instr),
|
|
|
|
.instr_is_32bit (decomp_instr_is_32bit),
|
|
.instr_out (decomp_instr_out),
|
|
|
|
.instr_out_is_uop (decomp_is_uop),
|
|
.instr_out_is_final_uop (decomp_is_final_uop),
|
|
.instr_out_uop_no_pc_update (decomp_uop_no_pc_update),
|
|
.instr_out_uop_atomic (decomp_uop_atomic),
|
|
.instr_out_uop_stall (uop_stall_non_first || uop_stall_on_repeat),
|
|
.instr_out_uop_clear (uop_clear),
|
|
.df_uop_step (decomp_uop_step),
|
|
|
|
.invalid (decomp_invalid)
|
|
);
|
|
|
|
wire cir_clken =
|
|
~|cir_vld || (!cir_vld[1] && &buf_contents[1:0]) ||
|
|
|cir_use || (|EXTENSION_ZCMP && cir_is_uop && !uop_stall) ||
|
|
(|EXTENSION_ZCMP && uop_clear);
|
|
|
|
wire cir_is_uop_next = decomp_is_uop && |buf_level_next;
|
|
wire cir_uop_nonfinal_next = cir_is_uop_next && !decomp_is_final_uop;
|
|
|
|
always @ (posedge clk or negedge rst_n) begin
|
|
if (!rst_n) begin
|
|
cir <= 32'd3;
|
|
cir_is_32bit <= 1'b0;
|
|
cir_invalid_16bit <= 1'b0;
|
|
cir_is_uop <= 1'b0;
|
|
cir_uop_nonfinal <= 1'b0;
|
|
cir_uop_no_pc_update <= 1'b0;
|
|
cir_uop_atomic <= 1'b0;
|
|
end else if (cir_clken) begin
|
|
cir <= decomp_instr_out | 32'd3;
|
|
cir_is_32bit <= decomp_instr_is_32bit;
|
|
cir_invalid_16bit <= decomp_invalid;
|
|
cir_is_uop <= |EXTENSION_ZCMP && !uop_clear && cir_is_uop_next;
|
|
cir_uop_nonfinal <= |EXTENSION_ZCMP && !uop_clear && cir_uop_nonfinal_next;
|
|
cir_uop_no_pc_update <= |EXTENSION_ZCMP && !uop_clear && decomp_uop_no_pc_update;
|
|
cir_uop_atomic <= |EXTENSION_ZCMP && !uop_clear && decomp_uop_atomic;
|
|
end
|
|
end
|
|
|
|
end
|
|
endgenerate
|
|
|
|
assign cir_raw = {
|
|
buf_contents[1 * W_SLOT +: W_BUNDLE],
|
|
buf_contents[0 * W_SLOT +: W_BUNDLE]
|
|
};
|
|
|
|
endmodule
|
|
|
|
`ifndef YOSYS
|
|
`default_nettype wire
|
|
`endif
|