53 lines
1.4 KiB
Verilog
53 lines
1.4 KiB
Verilog
/*****************************************************************************\
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| Copyright (C) 2022 Luke Wren |
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| SPDX-License-Identifier: Apache-2.0 |
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\*****************************************************************************/
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`default_nettype none
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// The branch decision path through the ALU is slow because:
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//
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// - Sees immediates and PC on its inputs, as well as regs
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// - Add/sub rather than just add (with complex decode of the sub condition)
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// - 2 extra mux layers in front of adder if Zba extension is enabled
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//
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// So there is sometimes timing benefit to a dedicated branch comparator.
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module hazard3_branchcmp #(
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`include "hazard3_config.vh"
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,
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`include "hazard3_width_const.vh"
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) (
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input wire [31:0] cir,
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input wire [W_DATA-1:0] op_a,
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input wire [W_DATA-1:0] op_b,
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output wire cmp
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);
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`include "hazard3_ops.vh"
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wire [W_DATA-1:0] diff = op_a - op_b;
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// funct3 instruction
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// ------------------
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// 000 BEQ
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// 001 BNE
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// 100 BLT
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// 101 BGE
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// 110 BLTU
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// 111 BGEU
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wire cmp_is_unsigned = cir[13];
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wire lt = op_a[W_DATA-1] == op_b[W_DATA-1] ? diff[W_DATA-1] :
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cmp_is_unsigned ? op_b[W_DATA-1] :
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op_a[W_DATA-1] ;
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assign cmp = cir[14] ? lt : op_a != op_b;
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endmodule
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`ifndef YOSYS
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`default_nettype wire
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`endif
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