feat: publish FreeRTOS C FC07 card
This commit is contained in:
@@ -0,0 +1,58 @@
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
|
||||
#define configCPU_CLOCK_HZ ( 10000000UL )
|
||||
#define configTICK_RATE_HZ ( 1000U )
|
||||
#define configMTIME_BASE_ADDRESS ( 0xC0000100UL )
|
||||
#define configMTIMECMP_BASE_ADDRESS ( 0xC0000108UL )
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_TIME_SLICING 1
|
||||
#define configNUMBER_OF_CORES 1
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
|
||||
#define configUSE_IDLE_HOOK 0
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configMAX_PRIORITIES 5
|
||||
#define configMINIMAL_STACK_SIZE 128
|
||||
#define configMAX_TASK_NAME_LEN 16
|
||||
#define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_32_BITS
|
||||
#define configIDLE_SHOULD_YIELD 1
|
||||
#define configSUPPORT_DYNAMIC_ALLOCATION 1
|
||||
#define configSUPPORT_STATIC_ALLOCATION 0
|
||||
#define configTOTAL_HEAP_SIZE ( 16U * 1024U )
|
||||
#define configAPPLICATION_ALLOCATED_HEAP 1
|
||||
#define configUSE_MALLOC_FAILED_HOOK 1
|
||||
#define configHEAP_CLEAR_MEMORY_ON_FREE 0
|
||||
#define configUSE_TIMERS 0
|
||||
#define configUSE_MUTEXES 0
|
||||
#define configUSE_RECURSIVE_MUTEXES 0
|
||||
#define configUSE_COUNTING_SEMAPHORES 0
|
||||
#define configUSE_TASK_NOTIFICATIONS 0
|
||||
#define configUSE_TRACE_FACILITY 1
|
||||
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
|
||||
#define configGENERATE_RUN_TIME_STATS 0
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configUSE_NEWLIB_REENTRANT 0
|
||||
#define configUSE_POSIX_ERRNO 0
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 0
|
||||
#define configRECORD_STACK_HIGH_ADDRESS 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_vTaskDelayUntil 0
|
||||
#define INCLUDE_vTaskDelete 1
|
||||
#define INCLUDE_vTaskSuspend 0
|
||||
#define INCLUDE_eTaskGetState 1
|
||||
#define INCLUDE_uxTaskPriorityGet 1
|
||||
#define INCLUDE_vTaskPrioritySet 0
|
||||
#define INCLUDE_xTaskGetSchedulerState 1
|
||||
#define INCLUDE_uxTaskGetStackHighWaterMark 1
|
||||
#define configENABLE_FPU 0
|
||||
#define configENABLE_VPU 0
|
||||
#define configISR_STACK_SIZE_WORDS 256
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
void lab_assert_fail( const char * file, int line );
|
||||
#define configASSERT( condition ) \
|
||||
do { if( !( condition ) ) { lab_assert_fail( __FILE__, __LINE__ ); } } while( 0 )
|
||||
#else
|
||||
#define configASSERT( condition )
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,15 @@
|
||||
#ifndef FREERTOS_RISC_V_CHIP_SPECIFIC_EXTENSIONS_H
|
||||
#define FREERTOS_RISC_V_CHIP_SPECIFIC_EXTENSIONS_H
|
||||
|
||||
/* Hazard3 adds no architectural registers to the base RV32I context. */
|
||||
#define portasmHAS_MTIME 1
|
||||
#define portasmHAS_SIFIVE_CLINT 0
|
||||
#define portasmADDITIONAL_CONTEXT_SIZE 0
|
||||
|
||||
.macro portasmSAVE_ADDITIONAL_REGISTERS
|
||||
.endm
|
||||
|
||||
.macro portasmRESTORE_ADDITIONAL_REGISTERS
|
||||
.endm
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,66 @@
|
||||
#ifndef _HAZARD3_CSR_H
|
||||
#define _HAZARD3_CSR_H
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include "stdint.h"
|
||||
#endif
|
||||
|
||||
#define hazard3_csr_dmdata0 0xbff // Debug-mode shadow CSR for DM data transfer
|
||||
|
||||
#define hazard3_csr_meiea 0xbe0 // External interrupt pending array
|
||||
#define hazard3_csr_meipa 0xbe1 // External interrupt enable array
|
||||
#define hazard3_csr_meifa 0xbe2 // External interrupt force array
|
||||
#define hazard3_csr_meipra 0xbe3 // External interrupt priority array
|
||||
#define hazard3_csr_meinext 0xbe4 // Next external interrupt
|
||||
#define hazard3_csr_meicontext 0xbe5 // External interrupt context register
|
||||
|
||||
#define hazard3_csr_msleep 0xbf0 // M-mode sleep control register
|
||||
|
||||
#define hazard3_csr_pmpcfgm0 0xbd0 // Non-locking M-mode enables for PMP regions
|
||||
|
||||
#define _read_csr(csrname) ({ \
|
||||
uint32_t __csr_tmp_u32; \
|
||||
__asm__ volatile ("csrr %0, " #csrname : "=r" (__csr_tmp_u32)); \
|
||||
__csr_tmp_u32; \
|
||||
})
|
||||
|
||||
#define _write_csr(csrname, data) ({ \
|
||||
__asm__ volatile ("csrw " #csrname ", %0" : : "r" (data)); \
|
||||
})
|
||||
|
||||
#define _set_csr(csrname, data) ({ \
|
||||
__asm__ volatile ("csrs " #csrname ", %0" : : "r" (data)); \
|
||||
})
|
||||
|
||||
#define _clear_csr(csrname, data) ({ \
|
||||
__asm__ volatile ("csrc " #csrname ", %0" : : "r" (data)); \
|
||||
})
|
||||
|
||||
#define _read_write_csr(csrname, data) ({ \
|
||||
uint32_t __csr_tmp_u32; \
|
||||
__asm__ volatile ("csrrw %0, " #csrname ", %1" : "=r" (__csr_tmp_u32) : "r" (data)); \
|
||||
__csr_tmp_u32; \
|
||||
})
|
||||
|
||||
#define _read_set_csr(csrname, data) ({ \
|
||||
uint32_t __csr_tmp_u32; \
|
||||
__asm__ volatile ("csrrs %0, " #csrname ", %1" : "=r" (__csr_tmp_u32) : "r" (data)); \
|
||||
__csr_tmp_u32; \
|
||||
})
|
||||
|
||||
#define _read_clear_csr(csrname, data) ({ \
|
||||
uint32_t __csr_tmp_u32; \
|
||||
__asm__ volatile ("csrrc %0, " #csrname ", %1" : "=r" (__csr_tmp_u32) : "r" (data)); \
|
||||
__csr_tmp_u32; \
|
||||
})
|
||||
|
||||
// Argument macro expansion layer
|
||||
#define read_csr(csrname) _read_csr(csrname)
|
||||
#define write_csr(csrname, data) _write_csr(csrname, data)
|
||||
#define set_csr(csrname, data) _set_csr(csrname, data)
|
||||
#define clear_csr(csrname, data) _clear_csr(csrname, data)
|
||||
#define read_write_csr(csrname, data) _read_write_csr(csrname, data)
|
||||
#define read_set_csr(csrname, data) _read_set_csr(csrname, data)
|
||||
#define read_clear_csr(csrname, data) _read_clear_csr(csrname, data)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,100 @@
|
||||
#ifndef _HAZARD3_IRQ_H
|
||||
#define _HAZARD3_IRQ_H
|
||||
|
||||
#include "hazard3_csr.h"
|
||||
#include "stdint.h"
|
||||
#include "stdbool.h"
|
||||
|
||||
// Should match processor configuration in testbench:
|
||||
#define NUM_IRQS 32
|
||||
#define MAX_PRIORITY 15
|
||||
|
||||
// Declarations for irq_dispatch.S
|
||||
extern uintptr_t _external_irq_table[NUM_IRQS];
|
||||
extern uint32_t _external_irq_entry_count;
|
||||
|
||||
#define h3irq_array_read(csr, index) (read_set_csr(csr, (index)) >> 16)
|
||||
|
||||
#define h3irq_array_write(csr, index, data) (write_csr(csr, (index) | ((uint32_t)(data) << 16)))
|
||||
#define h3irq_array_set(csr, index, data) (set_csr(csr, (index) | ((uint32_t)(data) << 16)))
|
||||
#define h3irq_array_clear(csr, index, data) (clear_csr(csr, (index) | ((uint32_t)(data) << 16)))
|
||||
|
||||
static inline void h3irq_enable(unsigned int irq, bool enable) {
|
||||
if (enable) {
|
||||
h3irq_array_set(hazard3_csr_meiea, irq >> 4, 1u << (irq & 0xfu));
|
||||
}
|
||||
else {
|
||||
h3irq_array_clear(hazard3_csr_meiea, irq >> 4, 1u << (irq & 0xfu));
|
||||
}
|
||||
}
|
||||
|
||||
static inline bool h3irq_pending(unsigned int irq) {
|
||||
return h3irq_array_read(hazard3_csr_meipa, irq >> 4) & (1u << (irq & 0xfu));
|
||||
}
|
||||
|
||||
static inline void h3irq_force_pending(unsigned int irq, bool force) {
|
||||
if (force) {
|
||||
h3irq_array_set(hazard3_csr_meifa, irq >> 4, 1u << (irq & 0xfu));
|
||||
}
|
||||
else {
|
||||
h3irq_array_clear(hazard3_csr_meifa, irq >> 4, 1u << (irq & 0xfu));
|
||||
}
|
||||
}
|
||||
|
||||
static inline bool h3irq_is_forced(unsigned int irq) {
|
||||
return h3irq_array_read(hazard3_csr_meifa, irq >> 4) & (1u << (irq & 0xfu));
|
||||
}
|
||||
|
||||
// -1 for no IRQ
|
||||
static inline int h3irq_get_current_irq() {
|
||||
uint32_t meicontext = read_csr(hazard3_csr_meicontext);
|
||||
return ( meicontext & 0x8000u ) != 0U
|
||||
? -1
|
||||
: ( int ) ( ( meicontext >> 4 ) & 0x1ffu );
|
||||
}
|
||||
|
||||
static inline void h3irq_set_priority(unsigned int irq, uint32_t priority) {
|
||||
// Don't want read-modify-write, but no instruction for atomically writing
|
||||
// a bitfield. So, first drop priority to minimum, then set to the target
|
||||
// value. It should be safe to drop an IRQ's priority below its current
|
||||
// even from within that IRQ (but it is never safe to boost an IRQ when
|
||||
// it may already be in an older stack frame)
|
||||
h3irq_array_clear(hazard3_csr_meipra, irq >> 2, 0xfu << (4 * (irq & 0x3)));
|
||||
h3irq_array_set(hazard3_csr_meipra, irq >> 2, (priority & 0xfu) << (4 * (irq & 0x3)));
|
||||
}
|
||||
|
||||
static inline void h3irq_set_handler(unsigned int irq, void (*handler)(void)) {
|
||||
_external_irq_table[irq] = (uintptr_t)handler;
|
||||
}
|
||||
|
||||
static inline void global_irq_enable(bool en) {
|
||||
// mstatus.mie
|
||||
if (en) {
|
||||
set_csr(mstatus, 0x8);
|
||||
}
|
||||
else {
|
||||
clear_csr(mstatus, 0x8);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void external_irq_enable(bool en) {
|
||||
// mie.meie
|
||||
if (en) {
|
||||
set_csr(mie, 0x800);
|
||||
}
|
||||
else {
|
||||
clear_csr(mie, 0x800);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void timer_irq_enable(bool en) {
|
||||
// mie.mtie
|
||||
if (en) {
|
||||
set_csr(mie, 0x080);
|
||||
}
|
||||
else {
|
||||
clear_csr(mie, 0x080);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,11 @@
|
||||
#ifndef LAB_FREESTANDING_STDLIB_H
|
||||
#define LAB_FREESTANDING_STDLIB_H
|
||||
|
||||
/*
|
||||
* The selected FreeRTOS sources include <stdlib.h> for standard types, but the
|
||||
* configuration used by this card does not call hosted stdlib functions.
|
||||
* GCC's freestanding headers provide size_t through <stddef.h>.
|
||||
*/
|
||||
#include <stddef.h>
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,17 @@
|
||||
#ifndef LAB_FREESTANDING_STRING_H
|
||||
#define LAB_FREESTANDING_STRING_H
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void * memcpy( void * destination, const void * source, size_t count );
|
||||
void * memset( void * destination, int value, size_t count );
|
||||
size_t strlen( const char * text );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,49 @@
|
||||
#ifndef TASK01_ISR_SEMAPHORE_H
|
||||
#define TASK01_ISR_SEMAPHORE_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "FreeRTOS.h"
|
||||
#include "semphr.h"
|
||||
#include "task.h"
|
||||
#include "task01_isr_semaphore_model.h"
|
||||
|
||||
#define FC07_IRQ_NUMBER 5U
|
||||
#define FC07_IRQ_MASK ( 1UL << FC07_IRQ_NUMBER )
|
||||
#define FC07_TASK_STACK_WORDS 256U
|
||||
#define FC07_WAITER_PRIORITY 3U
|
||||
#define FC07_STIMULUS_PRIORITY 2U
|
||||
#define FC07_VERIFIER_PRIORITY 1U
|
||||
#define FC07_EVENT_CAPACITY 10U
|
||||
#define FC07_TIMEOUT_TICKS 20U
|
||||
|
||||
typedef struct IsrExperiment
|
||||
{
|
||||
SemaphoreHandle_t semaphore;
|
||||
TaskHandle_t waiter;
|
||||
TaskHandle_t stimulus;
|
||||
TaskHandle_t verifier;
|
||||
uintptr_t waiter_sp;
|
||||
uintptr_t stimulus_sp;
|
||||
uintptr_t isr_sp;
|
||||
uint32_t mcause;
|
||||
uint32_t irq_source_after_clear;
|
||||
BaseType_t higher_priority_task_woken;
|
||||
uint32_t waiter_ran;
|
||||
uint32_t stimulus_after;
|
||||
uint32_t pass;
|
||||
uint32_t digest;
|
||||
} IsrExperiment;
|
||||
|
||||
extern IsrExperiment g_fc07;
|
||||
extern IsrEvidence g_fc07_events[ FC07_EVENT_CAPACITY ];
|
||||
extern volatile uint32_t g_fc07_event_count;
|
||||
extern volatile uint32_t g_fc07_last_checkpoint;
|
||||
extern volatile uint32_t g_fc07_pass;
|
||||
|
||||
void fc07_checkpoint_committed( uint32_t point, const void * subject );
|
||||
void freertos_risc_v_application_interrupt_handler( void );
|
||||
void fc07_waiter_entry( void * context );
|
||||
void fc07_stimulus_entry( void * context );
|
||||
void fc07_verifier_entry( void * context );
|
||||
#endif
|
||||
@@ -0,0 +1,52 @@
|
||||
#ifndef TASK01_ISR_SEMAPHORE_MODEL_H
|
||||
#define TASK01_ISR_SEMAPHORE_MODEL_H
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct IsrEvidence
|
||||
{
|
||||
uint32_t sequence;
|
||||
uint32_t event;
|
||||
uint32_t tick;
|
||||
uint32_t actor;
|
||||
uint32_t value;
|
||||
uint32_t committed;
|
||||
} IsrEvidence;
|
||||
|
||||
static inline int fc07_order_is_valid( const IsrEvidence * events,
|
||||
size_t count )
|
||||
{
|
||||
size_t index;
|
||||
if( count != 9U )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
for( index = 0U; index < count; ++index )
|
||||
{
|
||||
if( events[ index ].sequence != index + 1U ||
|
||||
events[ index ].event != index + 1U ||
|
||||
events[ index ].committed !=
|
||||
( 0xFC070000U | ( uint32_t ) ( index + 1U ) ) )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
static inline uint32_t fc07_digest( const IsrEvidence * events,
|
||||
size_t count )
|
||||
{
|
||||
uint32_t hash = 2166136261U;
|
||||
size_t index;
|
||||
for( index = 0U; index < count; ++index )
|
||||
{
|
||||
hash = ( hash ^ events[ index ].event ) * 16777619U;
|
||||
hash = ( hash ^ events[ index ].actor ) * 16777619U;
|
||||
hash = ( hash ^ events[ index ].value ) * 16777619U;
|
||||
hash = ( hash ^ events[ index ].committed ) * 16777619U;
|
||||
}
|
||||
return hash;
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user