44 lines
1.1 KiB
Makefile
44 lines
1.1 KiB
Makefile
# Must define:
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# DOTF: .f file containing root of file list
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# TOP: name of top-level module
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SRCS=$(shell PROJ_ROOT=$(PROJ_ROOT) HDL=$(HDL) $(SCRIPTS)/listfiles --relative -f flat $(DOTF))
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INCDIRS=$(shell PROJ_ROOT=$(PROJ_ROOT) HDL=$(HDL) $(SCRIPTS)/listfiles --relative -f flati $(DOTF))
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YOSYS=yosys
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YOSYS_SMTBMC=$(YOSYS)-smtbmc
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DEPTH?=20
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COVER_APPEND?=3
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YOSYS_SMT_SOLVER?=z3
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DEFINES?=
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PREP_CMD =read_verilog -formal
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PREP_CMD+=$(addprefix -I,$(INCDIRS))
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PREP_CMD+=$(addprefix -D,$(DEFINES) )
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PREP_CMD+= $(SRCS);
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PREP_CMD+=prep -top $(TOP); async2sync; dffunmap; write_smt2 -wires $(TOP).smt2
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BMC_ARGS=-s $(YOSYS_SMT_SOLVER) --dump-vcd $(TOP).vcd -t $(DEPTH)
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IND_ARGS=-i $(BMC_ARGS)
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COV_ARGS = -c $(BMC_ARGS) --append $(COVER_APPEND)
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.PHONY: prove prep bmc induct clean
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prove: bmc induct
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prep:
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$(YOSYS) -p "$(PREP_CMD)" > prep.log
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bmc: prep
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$(YOSYS_SMTBMC) $(BMC_ARGS) $(TOP).smt2 | tee bmc.log
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induct: prep
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$(YOSYS_SMTBMC) $(IND_ARGS) $(TOP).smt2 | tee induct.log
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cover: prep
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$(YOSYS_SMTBMC) $(COV_ARGS) $(TOP).smt2 | tee cover.log
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clean::
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rm -f $(TOP).vcd $(TOP).smt2 srcs.mk prep.log bmc.log induct.log cover.log
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