lab-rv32i-freertos-event-group/doc/card-plan.md

K13 — EventGroup and coordinated state

Position

• Series: FreeRTOS C++
• Lesson: L12, card K13
• Duration: 30 minutes
• Typed bits: UART=0x1, GPIO=0x2, APP=0x4
• Static control block; no heap delta

Outcome

The student designs a typed readiness mask, distinguishes any/all and keep/clear-on-exit, explains timeout snapshots, and rejects the interpretation of an event bit as a counter or payload.

Lesson plan

Time	Mode	Evidence
0–5	typed masks	enum bits combine to all=0x7
5–10	publishers	coordinator Blocked; workers set 1,2,4
10–15	wait all	snapshot/current=0x7, satisfied
15–20	clear one	clear GPIO returns 0x7, current=0x5
20–25	timeout	all unsatisfied for 3 ticks, snapshot=0x5
25–30	any + clear	snapshot=0x5, final=0; discuss races/counters

Acceptance

• type is an enum and masks remain typed at the wrapper boundary;
• event-group handle equals caller static control and heap delta is zero;
• coordinator is eBlocked before the first worker publishes;
• repeated UART set is idempotent at mask 1;
• all/keep gives 7 and explicit GPIO clear gives 5;
• second all wait times out after at least 3 ticks with snapshot 5;
• any/clear-on-exit succeeds with snapshot 5 and final mask 0;
• target exits with PASS.

Main traps

1. A bit is state, not an event count.
2. A bit mask is not a payload record.
3. Clear-on-exit affects all selected bits and can race with other waiters.
4. Timeout return is a snapshot; test satisfaction explicitly.
5. EventGroup FromISR set is deferred through the timer service task.