feat: add lab-rv32i-freertos-isr-drivers card
This commit is contained in:
user
@@ -0,0 +1,62 @@
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#ifndef FREERTOS_CONFIG_H
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#define FREERTOS_CONFIG_H
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#define configCPU_CLOCK_HZ ( 10000000UL )
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#define configTICK_RATE_HZ ( 1000U )
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#define configMTIME_BASE_ADDRESS ( 0xC0000100UL )
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#define configMTIMECMP_BASE_ADDRESS ( 0xC0000108UL )
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#define configUSE_PREEMPTION 1
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#define configUSE_TIME_SLICING 1
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#define configNUMBER_OF_CORES 1
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#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
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#define configUSE_IDLE_HOOK 0
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#define configUSE_TICK_HOOK 0
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#define configMAX_PRIORITIES 5
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#define configMINIMAL_STACK_SIZE 128
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#define configMAX_TASK_NAME_LEN 16
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#define configTICK_TYPE_WIDTH_IN_BITS TICK_TYPE_WIDTH_32_BITS
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#define configIDLE_SHOULD_YIELD 1
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#define configSUPPORT_DYNAMIC_ALLOCATION 1
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#define configSUPPORT_STATIC_ALLOCATION 1
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#define configKERNEL_PROVIDED_STATIC_MEMORY 1
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#define configTOTAL_HEAP_SIZE ( 16U * 1024U )
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#define configAPPLICATION_ALLOCATED_HEAP 1
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#define configUSE_MALLOC_FAILED_HOOK 1
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#define configHEAP_CLEAR_MEMORY_ON_FREE 0
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#define configUSE_TIMERS 0
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#define configUSE_MUTEXES 0
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#define configUSE_RECURSIVE_MUTEXES 0
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#define configUSE_COUNTING_SEMAPHORES 0
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#define configUSE_TASK_NOTIFICATIONS 1
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#define configUSE_TRACE_FACILITY 1
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#define configUSE_STATS_FORMATTING_FUNCTIONS 0
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#define configGENERATE_RUN_TIME_STATS 0
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#define configUSE_CO_ROUTINES 0
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#define configUSE_NEWLIB_REENTRANT 0
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#define configUSE_POSIX_ERRNO 0
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#define configCHECK_FOR_STACK_OVERFLOW 0
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#define configRECORD_STACK_HIGH_ADDRESS 1
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#define INCLUDE_vTaskDelay 1
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#define INCLUDE_vTaskDelayUntil 0
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#define INCLUDE_vTaskDelete 1
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#define INCLUDE_vTaskSuspend 0
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#define INCLUDE_eTaskGetState 1
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#define INCLUDE_uxTaskPriorityGet 1
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#define INCLUDE_vTaskPrioritySet 0
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#define INCLUDE_xTaskGetSchedulerState 1
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#define INCLUDE_uxTaskGetStackHighWaterMark 1
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#define configENABLE_FPU 0
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#define configENABLE_VPU 0
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#define configISR_STACK_SIZE_WORDS 256
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#ifndef __ASSEMBLER__
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#ifdef __cplusplus
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extern "C" void lab_assert_fail( const char * file, int line );
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#else
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void lab_assert_fail( const char * file, int line );
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#endif
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#define configASSERT( condition ) do { if( !( condition ) ) { lab_assert_fail( __FILE__, __LINE__ ); } } while( 0 )
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#else
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#define configASSERT( condition )
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#endif
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#endif
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@@ -0,0 +1,278 @@
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#ifndef FREERTOS_ISR_DRIVERS_HPP
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#define FREERTOS_ISR_DRIVERS_HPP
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#include <cstddef>
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#include <cstdint>
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#include <type_traits>
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extern "C"
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{
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#include "FreeRTOS.h"
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#include "queue.h"
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#include "task.h"
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}
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namespace freertos
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{
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class IsrContext final
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{
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public:
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void merge_wake_request( BaseType_t local_request ) noexcept
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{
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if( local_request != pdFALSE )
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{
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higher_priority_task_woken_ = pdTRUE;
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}
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}
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[[nodiscard]] bool wake_requested() const noexcept
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{
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return higher_priority_task_woken_ != pdFALSE;
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}
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[[nodiscard]] std::uint32_t yield_calls() const noexcept
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{
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return yield_calls_;
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}
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[[nodiscard]] bool yield_if_needed() noexcept
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{
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++yield_calls_;
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bool const requested = wake_requested();
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portYIELD_FROM_ISR( higher_priority_task_woken_ );
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return requested;
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}
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private:
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BaseType_t higher_priority_task_woken_{ pdFALSE };
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std::uint32_t yield_calls_{ 0U };
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};
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enum class IsrSendResult
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{
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queued,
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dropped_newest
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};
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template< typename T, std::size_t Capacity >
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class StaticIsrQueue final
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{
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static_assert( Capacity > 0U );
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static_assert( std::is_trivially_copyable_v< T > );
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public:
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StaticIsrQueue( StaticQueue_t & control, std::uint8_t * bytes ) noexcept
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: handle_( xQueueCreateStatic( static_cast< UBaseType_t >( Capacity ),
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static_cast< UBaseType_t >( sizeof( T ) ),
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bytes,
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&control ) )
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{
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}
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StaticIsrQueue( const StaticIsrQueue & ) = delete;
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StaticIsrQueue & operator=( const StaticIsrQueue & ) = delete;
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[[nodiscard]] bool valid() const noexcept
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{
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return handle_ != nullptr;
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}
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[[nodiscard]] IsrSendResult send_from_isr( const T & item,
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IsrContext & context ) noexcept
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{
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BaseType_t local_wake = pdFALSE;
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BaseType_t const result = xQueueSendFromISR( handle_, &item, &local_wake );
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context.merge_wake_request( local_wake );
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return result == pdPASS ? IsrSendResult::queued
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: IsrSendResult::dropped_newest;
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}
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[[nodiscard]] bool receive( T & item, TickType_t timeout ) noexcept
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{
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return xQueueReceive( handle_, &item, timeout ) == pdPASS;
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}
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private:
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QueueHandle_t handle_;
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};
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class TaskNotificationRef final
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{
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public:
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explicit constexpr TaskNotificationRef( TaskHandle_t task ) noexcept
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: task_( task )
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{
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}
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[[nodiscard]] bool give_from_isr( IsrContext & context ) const noexcept
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{
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BaseType_t local_wake = pdFALSE;
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vTaskNotifyGiveFromISR( task_, &local_wake );
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context.merge_wake_request( local_wake );
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return true;
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}
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private:
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TaskHandle_t task_;
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};
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struct UartRegisters
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{
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volatile std::uint32_t status;
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volatile std::uint32_t rx_data[ 2 ];
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volatile std::uint32_t rx_count;
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volatile std::uint32_t control;
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};
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class UartTaskView final
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{
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public:
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explicit constexpr UartTaskView( UartRegisters & registers ) noexcept
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: registers_( ®isters )
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{
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}
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void enable_rx_irq() const noexcept { registers_->control = 1U; }
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void inject_rx_pair_for_test( std::uint8_t first,
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std::uint8_t second ) const noexcept
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{
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registers_->rx_data[ 0 ] = first;
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registers_->rx_data[ 1 ] = second;
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registers_->rx_count = 2U;
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registers_->status = 1U;
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}
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private:
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UartRegisters * registers_;
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};
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class UartIsrView final
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{
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public:
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explicit constexpr UartIsrView( UartRegisters & registers ) noexcept
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: registers_( ®isters )
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{
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}
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[[nodiscard]] bool rx_ready_from_isr() const noexcept
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{
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return ( registers_->status & 1U ) != 0U &&
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registers_->rx_count != 0U;
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}
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[[nodiscard]] std::uint8_t read_rx_from_isr() const noexcept
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{
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configASSERT( rx_ready_from_isr() );
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std::uint8_t const byte =
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static_cast< std::uint8_t >( registers_->rx_data[ 0 ] );
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registers_->rx_data[ 0 ] = registers_->rx_data[ 1 ];
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--registers_->rx_count;
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if( registers_->rx_count == 0U )
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{
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registers_->status = 0U;
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}
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return byte;
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}
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private:
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UartRegisters * registers_;
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};
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class Uart final
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{
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public:
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explicit constexpr Uart( UartRegisters & registers ) noexcept
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: registers_( ®isters ) {}
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[[nodiscard]] UartTaskView task_view() const noexcept
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{
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return UartTaskView{ *registers_ };
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}
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[[nodiscard]] UartIsrView isr_view() const noexcept
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{
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return UartIsrView{ *registers_ };
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}
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private:
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UartRegisters * registers_;
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};
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struct GpioRegisters
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{
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volatile std::uint32_t direction;
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volatile std::uint32_t data;
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volatile std::uint32_t edge_status;
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};
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class GpioTaskView final
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{
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public:
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explicit constexpr GpioTaskView( GpioRegisters & registers ) noexcept
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: registers_( ®isters ) {}
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void configure_output( std::uint32_t mask ) const noexcept
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{
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registers_->direction |= mask;
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}
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void write_output( std::uint32_t mask, bool high ) const noexcept
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{
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if( high ) { registers_->data |= mask; }
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else { registers_->data &= ~mask; }
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}
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void inject_edge_for_test( std::uint32_t mask ) const noexcept
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{
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registers_->edge_status |= mask;
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}
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private:
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GpioRegisters * registers_;
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};
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class GpioIsrView final
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{
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public:
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explicit constexpr GpioIsrView( GpioRegisters & registers ) noexcept
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: registers_( ®isters ) {}
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[[nodiscard]] bool edge_pending_from_isr( std::uint32_t mask ) const noexcept
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{
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return ( registers_->edge_status & mask ) != 0U;
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}
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void clear_edge_from_isr( std::uint32_t mask ) const noexcept
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{
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registers_->edge_status &= ~mask;
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}
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private:
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GpioRegisters * registers_;
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};
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class GpioPin final
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{
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public:
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explicit constexpr GpioPin( GpioRegisters & registers ) noexcept
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: registers_( ®isters ) {}
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[[nodiscard]] GpioTaskView task_view() const noexcept
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{
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return GpioTaskView{ *registers_ };
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}
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[[nodiscard]] GpioIsrView isr_view() const noexcept
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{
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return GpioIsrView{ *registers_ };
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}
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private:
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GpioRegisters * registers_;
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};
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} // namespace freertos
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#endif
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@@ -0,0 +1,15 @@
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#ifndef FREERTOS_RISC_V_CHIP_SPECIFIC_EXTENSIONS_H
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#define FREERTOS_RISC_V_CHIP_SPECIFIC_EXTENSIONS_H
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/* Hazard3 adds no architectural registers to the base RV32I context. */
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#define portasmHAS_MTIME 1
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#define portasmHAS_SIFIVE_CLINT 0
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#define portasmADDITIONAL_CONTEXT_SIZE 0
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.macro portasmSAVE_ADDITIONAL_REGISTERS
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.endm
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.macro portasmRESTORE_ADDITIONAL_REGISTERS
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.endm
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#endif
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@@ -0,0 +1,66 @@
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#ifndef _HAZARD3_CSR_H
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#define _HAZARD3_CSR_H
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#ifndef __ASSEMBLER__
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#include "stdint.h"
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#endif
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#define hazard3_csr_dmdata0 0xbff // Debug-mode shadow CSR for DM data transfer
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#define hazard3_csr_meiea 0xbe0 // External interrupt pending array
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#define hazard3_csr_meipa 0xbe1 // External interrupt enable array
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#define hazard3_csr_meifa 0xbe2 // External interrupt force array
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#define hazard3_csr_meipra 0xbe3 // External interrupt priority array
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#define hazard3_csr_meinext 0xbe4 // Next external interrupt
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#define hazard3_csr_meicontext 0xbe5 // External interrupt context register
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#define hazard3_csr_msleep 0xbf0 // M-mode sleep control register
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#define hazard3_csr_pmpcfgm0 0xbd0 // Non-locking M-mode enables for PMP regions
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#define _read_csr(csrname) ({ \
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uint32_t __csr_tmp_u32; \
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__asm__ volatile ("csrr %0, " #csrname : "=r" (__csr_tmp_u32)); \
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__csr_tmp_u32; \
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})
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#define _write_csr(csrname, data) ({ \
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__asm__ volatile ("csrw " #csrname ", %0" : : "r" (data)); \
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})
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#define _set_csr(csrname, data) ({ \
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__asm__ volatile ("csrs " #csrname ", %0" : : "r" (data)); \
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})
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#define _clear_csr(csrname, data) ({ \
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__asm__ volatile ("csrc " #csrname ", %0" : : "r" (data)); \
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})
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#define _read_write_csr(csrname, data) ({ \
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uint32_t __csr_tmp_u32; \
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__asm__ volatile ("csrrw %0, " #csrname ", %1" : "=r" (__csr_tmp_u32) : "r" (data)); \
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__csr_tmp_u32; \
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})
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#define _read_set_csr(csrname, data) ({ \
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uint32_t __csr_tmp_u32; \
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__asm__ volatile ("csrrs %0, " #csrname ", %1" : "=r" (__csr_tmp_u32) : "r" (data)); \
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__csr_tmp_u32; \
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})
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#define _read_clear_csr(csrname, data) ({ \
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uint32_t __csr_tmp_u32; \
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__asm__ volatile ("csrrc %0, " #csrname ", %1" : "=r" (__csr_tmp_u32) : "r" (data)); \
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__csr_tmp_u32; \
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})
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// Argument macro expansion layer
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#define read_csr(csrname) _read_csr(csrname)
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#define write_csr(csrname, data) _write_csr(csrname, data)
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#define set_csr(csrname, data) _set_csr(csrname, data)
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#define clear_csr(csrname, data) _clear_csr(csrname, data)
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#define read_write_csr(csrname, data) _read_write_csr(csrname, data)
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#define read_set_csr(csrname, data) _read_set_csr(csrname, data)
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#define read_clear_csr(csrname, data) _read_clear_csr(csrname, data)
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#endif
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@@ -0,0 +1,100 @@
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#ifndef _HAZARD3_IRQ_H
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#define _HAZARD3_IRQ_H
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#include "hazard3_csr.h"
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#include "stdint.h"
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#include "stdbool.h"
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// Should match processor configuration in testbench:
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#define NUM_IRQS 32
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#define MAX_PRIORITY 15
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// Declarations for irq_dispatch.S
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extern uintptr_t _external_irq_table[NUM_IRQS];
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extern uint32_t _external_irq_entry_count;
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#define h3irq_array_read(csr, index) (read_set_csr(csr, (index)) >> 16)
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#define h3irq_array_write(csr, index, data) (write_csr(csr, (index) | ((uint32_t)(data) << 16)))
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#define h3irq_array_set(csr, index, data) (set_csr(csr, (index) | ((uint32_t)(data) << 16)))
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#define h3irq_array_clear(csr, index, data) (clear_csr(csr, (index) | ((uint32_t)(data) << 16)))
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static inline void h3irq_enable(unsigned int irq, bool enable) {
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if (enable) {
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h3irq_array_set(hazard3_csr_meiea, irq >> 4, 1u << (irq & 0xfu));
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}
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else {
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h3irq_array_clear(hazard3_csr_meiea, irq >> 4, 1u << (irq & 0xfu));
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}
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}
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static inline bool h3irq_pending(unsigned int irq) {
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return h3irq_array_read(hazard3_csr_meipa, irq >> 4) & (1u << (irq & 0xfu));
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}
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static inline void h3irq_force_pending(unsigned int irq, bool force) {
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if (force) {
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h3irq_array_set(hazard3_csr_meifa, irq >> 4, 1u << (irq & 0xfu));
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}
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else {
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h3irq_array_clear(hazard3_csr_meifa, irq >> 4, 1u << (irq & 0xfu));
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}
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}
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static inline bool h3irq_is_forced(unsigned int irq) {
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return h3irq_array_read(hazard3_csr_meifa, irq >> 4) & (1u << (irq & 0xfu));
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}
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// -1 for no IRQ
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static inline int h3irq_get_current_irq() {
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||||
uint32_t meicontext = read_csr(hazard3_csr_meicontext);
|
||||
return ( meicontext & 0x8000u ) != 0U
|
||||
? -1
|
||||
: ( int ) ( ( meicontext >> 4 ) & 0x1ffu );
|
||||
}
|
||||
|
||||
static inline void h3irq_set_priority(unsigned int irq, uint32_t priority) {
|
||||
// Don't want read-modify-write, but no instruction for atomically writing
|
||||
// a bitfield. So, first drop priority to minimum, then set to the target
|
||||
// value. It should be safe to drop an IRQ's priority below its current
|
||||
// even from within that IRQ (but it is never safe to boost an IRQ when
|
||||
// it may already be in an older stack frame)
|
||||
h3irq_array_clear(hazard3_csr_meipra, irq >> 2, 0xfu << (4 * (irq & 0x3)));
|
||||
h3irq_array_set(hazard3_csr_meipra, irq >> 2, (priority & 0xfu) << (4 * (irq & 0x3)));
|
||||
}
|
||||
|
||||
static inline void h3irq_set_handler(unsigned int irq, void (*handler)(void)) {
|
||||
_external_irq_table[irq] = (uintptr_t)handler;
|
||||
}
|
||||
|
||||
static inline void global_irq_enable(bool en) {
|
||||
// mstatus.mie
|
||||
if (en) {
|
||||
set_csr(mstatus, 0x8);
|
||||
}
|
||||
else {
|
||||
clear_csr(mstatus, 0x8);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void external_irq_enable(bool en) {
|
||||
// mie.meie
|
||||
if (en) {
|
||||
set_csr(mie, 0x800);
|
||||
}
|
||||
else {
|
||||
clear_csr(mie, 0x800);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void timer_irq_enable(bool en) {
|
||||
// mie.mtie
|
||||
if (en) {
|
||||
set_csr(mie, 0x080);
|
||||
}
|
||||
else {
|
||||
clear_csr(mie, 0x080);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,11 @@
|
||||
#ifndef LAB_FREESTANDING_STDLIB_H
|
||||
#define LAB_FREESTANDING_STDLIB_H
|
||||
|
||||
/*
|
||||
* The selected FreeRTOS sources include <stdlib.h> for standard types, but the
|
||||
* configuration used by this card does not call hosted stdlib functions.
|
||||
* GCC's freestanding headers provide size_t through <stddef.h>.
|
||||
*/
|
||||
#include <stddef.h>
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,17 @@
|
||||
#ifndef LAB_FREESTANDING_STRING_H
|
||||
#define LAB_FREESTANDING_STRING_H
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void * memcpy( void * destination, const void * source, size_t count );
|
||||
void * memset( void * destination, int value, size_t count );
|
||||
size_t strlen( const char * text );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user