feat: add lab-rv32i-freertos-sw-timer card

2026-07-21 19:14:20 +02:00
commit ae65adee32
172 changed files with 57117 additions and 0 deletions
@@ -0,0 +1,48 @@
+OUTPUT_FORMAT("elf32-littleriscv")
+OUTPUT_ARCH(riscv)
+ENTRY(_start)
+
+SECTIONS
+{
+  /* Hazard3 testbench RAM window */
+  . = 0x80000000;
+  PROVIDE(__stack_top = 0x80100000);
+
+  /* Reset/trap vectors are in Hazard3 init.S (.vectors). Keep them first so
+     .reset_handler lands at 0x80000040 (Hazard3 RESET_VECTOR). */
+  .text : ALIGN(4)
+  {
+    KEEP(*(.vectors))
+    *(.text .text.*)
+  }
+
+  /* Keep constants non-executable.  Merging arbitrary-length strings into
+     .text makes some RISC-V objdump versions try to decode the final partial
+     instruction and abort instead of producing the teaching listing. */
+  .rodata : ALIGN(4)
+  {
+    *(.rodata .rodata.*)
+  }
+
+  .data : ALIGN(4)
+  {
+    __data_start = .;
+    *(.data .data.*)
+    *(.sdata .sdata.*)
+    __data_end = .;
+  }
+
+  .bss : ALIGN(4)
+  {
+    __bss_start = .;
+    *(.bss .bss.* COMMON)
+    *(.sbss .sbss.*)
+    __bss_end = .;
+  }
+
+  /* Conservative default (good enough for this ASM-only demo). */
+  __global_pointer$ = __data_start + 0x800;
+
+  _end = .;
+  PROVIDE(end = .);
+}