feat(L07): add addresses and memory card

2026-07-21 17:14:02 +02:00
commit 529e720f5d
42 changed files with 7220 additions and 0 deletions
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+schema: 1
+card: rv32i-asm/L07
+title: Addresses and Memory
+steps:
+  - id: upper-immediate
+    task: task01_upper_immediate
+    action: test
+    profile: hazard3-sim
+    target: hazard3-baremetal
+    command: stemctl test hazard3-sim rv32i-asm L07 1
+    board:
+      show: [pc, imm20, upper_value, lui_result, auipc_result]
+      highlight: [bits_31_12, pc_relative_add]
+      question: Dlaczego AUIPC dla PC=0x100 daje wynik o 0x100 większy od LUI?
+    evidence: [lui_value, auipc_value]
+  - id: word-ram
+    task: task02_word_ram
+    action: debug
+    profile: hazard3-sim
+    target: hazard3-baremetal
+    command: stemctl debug hazard3-sim rv32i-asm L07 2
+    board:
+      show: [byte_address, word_index, write_enable, read_data, aligned, waveform]
+      highlight: [address_bits_5_2, alignment_bits_1_0]
+      question: Które bity adresu wybierają słowo, a które muszą być zerem?
+    evidence: [word0, word1, rejected_misaligned, trace_vcd]
+  - id: address-path
+    task: task03_address_memory_path
+    action: debug
+    profile: hazard3-sim
+    target: hazard3-baremetal
+    command: stemctl debug hazard3-sim rv32i-asm L07 3
+    board:
+      show: [base, signed_immediate, effective_address, ram_data, fault, waveform]
+      highlight: [address_adder, aligned_write, readback]
+      question: Jaki adres powstanie dla base=0x20 i immediate=12?
+    evidence: [effective_address, readback, alignment_fault, trace_vcd]