feat(L07): add addresses and memory card

src/tasks/task01_upper_immediate.sv

@@ -0,0 +1,12 @@
+module upper_immediate (
+    input logic [31:0] pc,
+    input logic [19:0] imm20,
+    input logic auipc,
+    output logic [31:0] result
+);
+    logic [31:0] upper_value;
+    always_comb begin
+        upper_value = {imm20, 12'b0};
+        result = auipc ? pc + upper_value : upper_value;
+    end
+endmodule

src/tasks/task02_word_ram.sv

@@ -0,0 +1,18 @@
+module word_ram (
+    input logic clk,
+    input logic request,
+    input logic write_enable,
+    input logic [31:0] byte_address,
+    input logic [31:0] write_data,
+    output logic [31:0] read_data,
+    output logic aligned,
+    output logic fault
+);
+    logic [31:0] memory [0:15];
+    assign aligned = byte_address[1:0] == 2'b00;
+    assign fault = request && !aligned;
+    assign read_data = request && aligned ? memory[byte_address[5:2]] : 32'b0;
+    always_ff @(posedge clk)
+        if (request && write_enable && aligned)
+            memory[byte_address[5:2]] <= write_data;
+endmodule

src/tasks/task03_address_memory_path.sv

@@ -0,0 +1,21 @@
+module address_memory_path (
+    input logic clk,
+    input logic request,
+    input logic write_enable,
+    input logic [31:0] base,
+    input logic signed [31:0] immediate,
+    input logic [31:0] write_data,
+    output logic [31:0] effective_address,
+    output logic [31:0] read_data,
+    output logic fault
+);
+    logic [31:0] memory [0:15];
+    always_comb begin
+        effective_address = base + immediate;
+        fault = request && effective_address[1:0] != 2'b00;
+        read_data = request && !fault ? memory[effective_address[5:2]] : 32'b0;
+    end
+    always_ff @(posedge clk)
+        if (request && write_enable && !fault)
+            memory[effective_address[5:2]] <= write_data;
+endmodule