module tb;
    logic clk = 0, request = 0, write_enable = 0;
    logic [31:0] base = 0, write_data = 0, effective_address, read_data;
    logic signed [31:0] immediate = 0;
    logic fault;
    string trace_file;
    address_memory_path dut (.*);
    always #1 clk = ~clk;
    initial begin
        if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
        @(negedge clk); request=1; write_enable=1; base=32'h20; immediate=12; write_data=32'hdeadbeef;
        @(posedge clk); #1;
        if (effective_address !== 32'h2c || fault) $fatal(1, "FAIL address=%h fault=%b", effective_address, fault);
        write_enable=0; #1; if (read_data !== 32'hdeadbeef) $fatal(1, "FAIL load=%h", read_data);
        immediate=2; #1; if (!fault || read_data !== 0) $fatal(1, "FAIL fault=%b data=%h", fault, read_data);
        $display("PASS task03 address=0000002c load=deadbeef fault=1");
        $finish;
    end
endmodule