user
38 lines
1.4 KiB
YAML
38 lines
1.4 KiB
YAML
schema: 1
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card: rv32i-asm/L07
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title: Addresses and Memory
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steps:
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- id: upper-immediate
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task: task01_upper_immediate
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action: test
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl test hazard3-sim rv32i-asm L07 1
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board:
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show: [pc, imm20, upper_value, lui_result, auipc_result]
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highlight: [bits_31_12, pc_relative_add]
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question: Dlaczego AUIPC dla PC=0x100 daje wynik o 0x100 większy od LUI?
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evidence: [lui_value, auipc_value]
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- id: word-ram
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task: task02_word_ram
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action: debug
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl debug hazard3-sim rv32i-asm L07 2
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board:
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show: [byte_address, word_index, write_enable, read_data, aligned, waveform]
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highlight: [address_bits_5_2, alignment_bits_1_0]
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question: Które bity adresu wybierają słowo, a które muszą być zerem?
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evidence: [word0, word1, rejected_misaligned, trace_vcd]
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- id: address-path
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task: task03_address_memory_path
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action: debug
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl debug hazard3-sim rv32i-asm L07 3
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board:
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show: [base, signed_immediate, effective_address, ram_data, fault, waveform]
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highlight: [address_adder, aligned_write, readback]
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question: Jaki adres powstanie dla base=0x20 i immediate=12?
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evidence: [effective_address, readback, alignment_fault, trace_vcd]
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