Files
lab-rv32i-asm-addresses-memory/tests/task01_upper_immediate_tb.sv
T
2026-07-21 17:14:02 +02:00

17 lines
575 B
Systemverilog

module tb;
logic [31:0] pc, result;
logic [19:0] imm20;
logic auipc;
string trace_file;
upper_immediate dut (.*);
initial begin
if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
pc = 32'h100; imm20 = 20'h12345; auipc = 0; #1;
if (result !== 32'h12345000) $fatal(1, "FAIL lui=%h", result);
auipc = 1; #1;
if (result !== 32'h12345100) $fatal(1, "FAIL auipc=%h", result);
$display("PASS task01 lui=12345000 auipc=12345100");
$finish;
end
endmodule