user
26 lines
1.2 KiB
Systemverilog
26 lines
1.2 KiB
Systemverilog
module tb;
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logic clk = 0, request = 0, write_enable = 0;
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logic [31:0] byte_address = 0, write_data = 0, read_data;
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logic aligned, fault;
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string trace_file;
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word_ram dut (.*);
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always #1 clk = ~clk;
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task automatic write_word(input logic [31:0] address, input logic [31:0] data);
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@(negedge clk); request=1; write_enable=1; byte_address=address; write_data=data;
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@(posedge clk); #1;
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endtask
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initial begin
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if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
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write_word(0, 32'h11223344); write_word(4, 32'haabbccdd);
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@(negedge clk); write_enable=0; byte_address=0; #1;
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if (read_data !== 32'h11223344 || !aligned || fault) $fatal(1, "FAIL word0=%h", read_data);
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byte_address=4; #1; if (read_data !== 32'haabbccdd) $fatal(1, "FAIL word1=%h", read_data);
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byte_address=2; write_enable=1; write_data=32'hffffffff; #1;
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if (!fault || aligned) $fatal(1, "FAIL misaligned flags");
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@(posedge clk); #1; write_enable=0; byte_address=0; #1;
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if (read_data !== 32'h11223344) $fatal(1, "FAIL misaligned modified memory");
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$display("PASS task02 word0=11223344 word1=aabbccdd misaligned=1");
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$finish;
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end
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endmodule
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