user
20 lines
957 B
Systemverilog
20 lines
957 B
Systemverilog
module tb;
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logic clk = 0, request = 0, write_enable = 0;
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logic [31:0] base = 0, write_data = 0, effective_address, read_data;
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logic signed [31:0] immediate = 0;
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logic fault;
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string trace_file;
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address_memory_path dut (.*);
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always #1 clk = ~clk;
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initial begin
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if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
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@(negedge clk); request=1; write_enable=1; base=32'h20; immediate=12; write_data=32'hdeadbeef;
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@(posedge clk); #1;
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if (effective_address !== 32'h2c || fault) $fatal(1, "FAIL address=%h fault=%b", effective_address, fault);
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write_enable=0; #1; if (read_data !== 32'hdeadbeef) $fatal(1, "FAIL load=%h", read_data);
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immediate=2; #1; if (!fault || read_data !== 0) $fatal(1, "FAIL fault=%b data=%h", fault, read_data);
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$display("PASS task03 address=0000002c load=deadbeef fault=1");
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$finish;
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end
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endmodule
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