module alu_core (
    input logic [31:0] operand_a, operand_b,
    input logic [3:0] operation,
    output logic [31:0] result,
    output logic zero
);
    localparam logic [3:0] ADD=0, SUB=1, AND_OP=2, OR_OP=3, XOR_OP=4,
        SLL_OP=5, SRL_OP=6, SRA_OP=7, SLT_OP=8, SLTU_OP=9;
    always_comb begin
        unique case (operation)
            ADD:     result = operand_a + operand_b;
            SUB:     result = operand_a - operand_b;
            AND_OP:  result = operand_a & operand_b;
            OR_OP:   result = operand_a | operand_b;
            XOR_OP:  result = operand_a ^ operand_b;
            SLL_OP:  result = operand_a << operand_b[4:0];
            SRL_OP:  result = operand_a >> operand_b[4:0];
            SRA_OP:  result = $signed(operand_a) >>> operand_b[4:0];
            SLT_OP:  result = {31'b0, $signed(operand_a) < $signed(operand_b)};
            SLTU_OP: result = {31'b0, operand_a < operand_b};
            default: result = 32'b0;
        endcase
    end
    assign zero = result == 0;
endmodule