schema: 1
card: rv32i-asm/L05
title: ALU and the Verilog Assembler
steps:
  - id: alu-vectors
    task: task01_alu_core
    action: debug
    profile: hazard3-sim
    target: hazard3-baremetal
    command: stemctl debug hazard3-sim rv32i-asm L05 1
    board:
      show: [operand_a, operand_b, operation, result, zero, waveform]
      highlight: [signed-vs-unsigned, shift-amount-5bits]
      question: Dlaczego SLT i SLTU mogą dać różne wyniki dla tych samych bitów?
    evidence: [ten_operations, signed_comparison, trace_vcd]
  - id: instruction-encoder
    task: task02_verilog_assembler
    action: test
    profile: hazard3-sim
    target: hazard3-baremetal
    command: stemctl test hazard3-sim rv32i-asm L05 2
    board:
      show: [format, fields, instruction]
      highlight: [r_type_layout, i_type_layout, immediate-low-12]
      question: Które pola rozróżniają ADD i SUB?
    evidence: [add_encoding, addi_negative_encoding]
  - id: execute-program
    task: task03_execute_stage
    action: debug
    profile: hazard3-sim
    target: hazard3-baremetal
    command: stemctl debug hazard3-sim rv32i-asm L05 3
    board:
      show: [instruction, rs1, rs2, alu_result, rd, write_enable, waveform]
      highlight: [addi, add, sub, writeback]
      question: Z których wcześniejszych wyników korzysta instrukcja SUB?
    evidence: [four_encodings, x1, x2, x3, x4, trace_vcd]