module tb;
    logic format_i; logic [4:0] rd,rs1,rs2; logic [2:0] funct3; logic [6:0] funct7; logic signed [11:0] immediate; logic [31:0] instruction; string trace_file;
    verilog_assembler dut (.*);
    initial begin
        if ($value$plusargs("trace=%s",trace_file)) begin $dumpfile(trace_file); $dumpvars(0,tb); end
        format_i=0; rd=3; rs1=1; rs2=2; funct3=0; funct7=0; immediate=0; #1; if(instruction!==32'h002081b3)$fatal(1,"FAIL add=%h",instruction);
        format_i=1; rd=5; rs1=6; rs2=0; funct3=0; funct7=0; immediate=-4; #1; if(instruction!==32'hffc30293)$fatal(1,"FAIL addi=%h",instruction);
        $display("PASS task02 add=002081b3 addi_neg4=ffc30293"); $finish;
    end
endmodule