user
38 lines
1.4 KiB
YAML
38 lines
1.4 KiB
YAML
schema: 1
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card: rv32i-asm/L05
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title: ALU and the Verilog Assembler
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steps:
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- id: alu-vectors
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task: task01_alu_core
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action: debug
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl debug hazard3-sim rv32i-asm L05 1
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board:
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show: [operand_a, operand_b, operation, result, zero, waveform]
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highlight: [signed-vs-unsigned, shift-amount-5bits]
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question: Dlaczego SLT i SLTU mogą dać różne wyniki dla tych samych bitów?
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evidence: [ten_operations, signed_comparison, trace_vcd]
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- id: instruction-encoder
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task: task02_verilog_assembler
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action: test
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl test hazard3-sim rv32i-asm L05 2
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board:
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show: [format, fields, instruction]
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highlight: [r_type_layout, i_type_layout, immediate-low-12]
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question: Które pola rozróżniają ADD i SUB?
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evidence: [add_encoding, addi_negative_encoding]
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- id: execute-program
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task: task03_execute_stage
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action: debug
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl debug hazard3-sim rv32i-asm L05 3
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board:
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show: [instruction, rs1, rs2, alu_result, rd, write_enable, waveform]
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highlight: [addi, add, sub, writeback]
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question: Z których wcześniejszych wyników korzysta instrukcja SUB?
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evidence: [four_encodings, x1, x2, x3, x4, trace_vcd]
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