user
14 lines
899 B
Systemverilog
14 lines
899 B
Systemverilog
module tb;
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logic [31:0] operand_a, operand_b, result; logic [3:0] operation; logic zero; integer checks=0; string trace_file;
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alu_core dut (.*);
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task automatic check(input logic [3:0] op, input logic [31:0] a, b, expected);
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operation=op; operand_a=a; operand_b=b; #1; if (result !== expected) $fatal(1,"FAIL task01 op=%0d got=%h expected=%h",op,result,expected); checks+=1;
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endtask
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initial begin
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if ($value$plusargs("trace=%s",trace_file)) begin $dumpfile(trace_file); $dumpvars(0,tb); end
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check(0,7,5,12); check(1,7,5,2); check(2,'ha5,'h3c,'h24); check(3,'ha5,'h3c,'hbd); check(4,'ha5,'h3c,'h99);
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check(5,1,4,16); check(6,'h80000000,4,'h08000000); check(7,'h80000000,4,'hf8000000); check(8,'h80000000,1,1); check(9,'h80000000,1,0);
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$display("PASS task01 ops=%0d signed_lt=1 unsigned_lt=0 sra=f8000000",checks); $finish;
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end
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endmodule
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