schema: 1
card: rv32i-asm/L03
title: Blinker and Synchronous Logic
steps:
  - id: clock-enable
    task: task01_clock_enable
    action: test
    profile: hazard3-sim
    target: hazard3-baremetal
    command: stemctl test hazard3-sim rv32i-asm L03 1
    board:
      show: [source, clock, reset, counter, enable]
      highlight: [posedge, synchronous-reset, terminal-count]
      question: W którym takcie enable może przyjąć wartość 1?
    evidence: [cycle, counter_before, enable_after]
  - id: counter-divider
    task: task02_counter_blinker
    action: debug
    profile: hazard3-sim
    target: hazard3-baremetal
    command: stemctl debug hazard3-sim rv32i-asm L03 2
    board:
      show: [source, waveform, counter, led]
      highlight: [counter_tap, half_period]
      question: Dlaczego wyższy bit licznika zmienia stan rzadziej?
    evidence: [counter_sequence, led_edges, trace_vcd]
  - id: pattern-rom
    task: task03_pattern_rom
    action: debug
    profile: hazard3-sim
    target: hazard3-baremetal
    command: stemctl debug hazard3-sim rv32i-asm L03 3
    board:
      show: [source, waveform, phase, pattern, led]
      highlight: [rom_index, wraparound]
      question: Jaki wzorzec pojawi się po fazie 7?
    evidence: [phase_sequence, led_sequence, wraparound, trace_vcd]