module tb;
    logic clk = 0;
    logic rst = 1;
    logic led;
    logic [3:0] count;
    integer edge_count = 0;
    integer expected_edges [0:3] = '{4, 8, 12, 16};
    logic previous = 0;
    string trace_file;

    counter_blinker dut (.*);
    always #1 clk = ~clk;

    initial begin
        if ($value$plusargs("trace=%s", trace_file)) begin
            $dumpfile(trace_file);
            $dumpvars(0, tb);
        end
        repeat (2) @(posedge clk);
        @(negedge clk);
        rst = 0;
        for (integer cycle = 1; cycle <= 16; cycle += 1) begin
            @(posedge clk); #1;
            if (led != previous) begin
                if (cycle != expected_edges[edge_count])
                    $fatal(1, "FAIL task02 edge=%0d cycle=%0d", edge_count, cycle);
                edge_count += 1;
            end
            if (led != count[2]) $fatal(1, "FAIL task02 led/count mismatch");
            previous = led;
        end
        if (edge_count != 4) $fatal(1, "FAIL task02 edge_count=%0d", edge_count);
        $display("PASS task02 led_edges=4,8,12,16 period=8");
        $finish;
    end
endmodule