module tb;
    logic clk = 0;
    logic rst = 1;
    logic step = 0;
    logic [2:0] phase;
    logic [3:0] led;
    logic [3:0] expected [0:9] = '{1, 2, 4, 8, 8, 4, 2, 1, 1, 2};
    string trace_file;

    pattern_rom dut (.*);
    always #1 clk = ~clk;

    initial begin
        if ($value$plusargs("trace=%s", trace_file)) begin
            $dumpfile(trace_file);
            $dumpvars(0, tb);
        end
        repeat (2) @(posedge clk);
        @(negedge clk);
        rst = 0;
        for (integer index = 0; index < 10; index += 1) begin
            if (led != expected[index])
                $fatal(1, "FAIL task03 index=%0d phase=%0d led=%0h expected=%0h", index, phase, led, expected[index]);
            step = 1;
            @(posedge clk); #1;
            step = 0;
            @(negedge clk);
        end
        $display("PASS task03 pattern=1,2,4,8,8,4,2,1 wrap=1,2");
        $finish;
    end
endmodule