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\begin{document}
\sloppy

\vspace{1.0em}
\noindent{\Large\bfseries Cel karty}\par
\vspace{0.35em}
Uczeń projektuje trzy syntezowalne moduły synchroniczne i dowodzi ich zachowania na podstawie modelu referencyjnego, self-checking testbencha i przebiegu VCD.

\vspace{0.8em}
\noindent\textcolor{black!25}{\rule{\textwidth}{0.35pt}}
\vspace{0.7em}
\noindent{\Large\bfseries Zakres tasków}\par
\vspace{0.35em}

\vspace{0.55em}
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\textbf{Krok} & \textbf{Numer tasku} & \textbf{Najważniejsza idea} & \textbf{Priorytet} & \textbf{Status} & \textbf{Version} \\ \hline
\texttt{1} & \texttt{Task01} & impuls clock enable & obowiązkowe & opracowane & \texttt{v00.01} \\ \hline
\texttt{2} & \texttt{Task02} & dzielnik przez bit licznika & obowiązkowe & opracowane & \texttt{v00.01} \\ \hline
\texttt{3} & \texttt{Task03} & ROM wzorca i zawijanie fazy & obowiązkowe & opracowane & \texttt{v00.01} \\ \hline
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\section{Task01 · Impuls clock enable}
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\begingroup
\scriptsize\ttfamily\color{black!60}\sloppy
\noindent drzewka: \pdftooltip[width=\textwidth]{D1}{RV03.WE01.OG.IP.01 | WE 01: Logika synchroniczna. Zaprojektowanie i zweryfikowanie\textCR deterministycznego toru synchronicznego. | EN IP WO RV03.01: Uczeń analizuje sekwencję\textCR stanów. | KW IP WS RV03.01: Sekwencja modelu i RTL jest zgodna.} \pdftooltip[width=\textwidth]{D2}{RV03.WE01.TECH.I4.01 | WE 01: Logika synchroniczna. Zaprojektowanie i zweryfikowanie\textCR deterministycznego toru synchronicznego. | EK INF04 RV03.01: Uczeń tworzy i testuje RTL. |\textCR KW INF04 RV03.01: Testbench kończy się PASS i zapisuje VCD.}\par
\vspace{0.10em}%
\noindent K1: Zapisz przewidywane takty impulsów w answers/blinker-evidence.md.\quad D1\par
\ESCTinyStepSeparator
\noindent K2: Uruchom oba profile i porównaj pulses oraz consecutive.\quad D2\par
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Przewidź wartość licznika przed każdym zboczem. Reset i licznik są synchroniczne. Impuls enable ma wartość 1 wyłącznie w takcie, w którym poprzedni stan licznika osiągnął DIVISOR-1.
\begin{figure}[H]
  \centering
  \includegraphics[width=0.9\linewidth]{\detokenize{../assets/blinker-flow.png}}
  \caption{Tor synchroniczny: zegar, licznik, faza/ROM i obserwowany LED.}
  \label{fig:blinker-flow}
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\section{Task02 · Licznik jako dzielnik}
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\begingroup
\scriptsize\ttfamily\color{black!60}\sloppy
\noindent drzewka: \pdftooltip[width=\textwidth]{D1}{RV03.WE01.OG.IP.01 | WE 01: Logika synchroniczna. Zaprojektowanie i zweryfikowanie\textCR deterministycznego toru synchronicznego. | EN IP WO RV03.01: Uczeń analizuje sekwencję\textCR stanów. | KW IP WS RV03.01: Sekwencja modelu i RTL jest zgodna.} \pdftooltip[width=\textwidth]{D2}{RV03.WE01.TECH.I4.01 | WE 01: Logika synchroniczna. Zaprojektowanie i zweryfikowanie\textCR deterministycznego toru synchronicznego. | EK INF04 RV03.01: Uczeń tworzy i testuje RTL. |\textCR KW INF04 RV03.01: Testbench kończy się PASS i zapisuje VCD.}\par
\vspace{0.10em}%
\noindent K1: Zapisz VCD i wskaż takty czterech zmian LED.\quad D1 D2\par
\par\vspace{0.18em}%
\endgroup

Dla licznika binarnego bit k ma okres \(2^{k+1}\) taktów. Zmierz dokładne zbocza \texttt{count[2]}, nie oceniaj częstotliwości na oko.
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\section{Task03 · Wzorzec ROM}
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\begingroup
\scriptsize\ttfamily\color{black!60}\sloppy
\noindent drzewka: \pdftooltip[width=\textwidth]{D1}{RV03.WE01.OG.IP.01 | WE 01: Logika synchroniczna. Zaprojektowanie i zweryfikowanie\textCR deterministycznego toru synchronicznego. | EN IP WO RV03.01: Uczeń analizuje sekwencję\textCR stanów. | KW IP WS RV03.01: Sekwencja modelu i RTL jest zgodna.} \pdftooltip[width=\textwidth]{D2}{RV03.WE01.TECH.I4.01 | WE 01: Logika synchroniczna. Zaprojektowanie i zweryfikowanie\textCR deterministycznego toru synchronicznego. | EK INF04 RV03.01: Uczeń tworzy i testuje RTL. |\textCR KW INF04 RV03.01: Testbench kończy się PASS i zapisuje VCD.}\par
\vspace{0.10em}%
\noindent K1: Porównaj dziesięć wartości LED i wyjaśnij zawinięcie fazy.\quad D1 D2\par
\par\vspace{0.18em}%
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Osiem stanów fazy adresuje stały wzorzec LED. Pomiar obejmuje dziesięć wartości, dlatego jawnie dowodzi zawinięcia 7 do 0.
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\end{document}