user
33 lines
924 B
Systemverilog
33 lines
924 B
Systemverilog
module tb;
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logic clk = 0;
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logic rst = 1;
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logic step = 0;
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logic [2:0] phase;
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logic [3:0] led;
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logic [3:0] expected [0:9] = '{1, 2, 4, 8, 8, 4, 2, 1, 1, 2};
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string trace_file;
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pattern_rom dut (.*);
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always #1 clk = ~clk;
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initial begin
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if ($value$plusargs("trace=%s", trace_file)) begin
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$dumpfile(trace_file);
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$dumpvars(0, tb);
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end
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repeat (2) @(posedge clk);
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@(negedge clk);
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rst = 0;
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for (integer index = 0; index < 10; index += 1) begin
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if (led != expected[index])
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$fatal(1, "FAIL task03 index=%0d phase=%0d led=%0h expected=%0h", index, phase, led, expected[index]);
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step = 1;
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@(posedge clk); #1;
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step = 0;
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@(negedge clk);
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end
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$display("PASS task03 pattern=1,2,4,8,8,4,2,1 wrap=1,2");
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$finish;
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end
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endmodule
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