user
23 lines
880 B
Systemverilog
23 lines
880 B
Systemverilog
module tb;
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logic [31:0] lhs, rhs;
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logic [2:0] funct3;
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logic taken, illegal;
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integer checks = 0;
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string trace_file;
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branch_compare dut (.*);
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task automatic check(input logic [2:0] function_code, input logic expected);
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funct3 = function_code; #1;
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if (taken !== expected || illegal) $fatal(1, "FAIL f=%b taken=%b illegal=%b", function_code, taken, illegal);
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checks += 1;
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endtask
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initial begin
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if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
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lhs = 32'hffffffff; rhs = 1;
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check(0,0); check(1,1); check(4,1); check(5,0); check(6,0); check(7,1);
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funct3 = 2; #1;
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if (!illegal || taken) $fatal(1, "FAIL illegal");
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$display("PASS task01 conditions=%0d signed_lt=1 unsigned_lt=0 illegal=1", checks);
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$finish;
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end
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endmodule
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