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lab-rv32i-asm-control-flow/tests/task02_control_immediate_tb.sv
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Systemverilog

module tb;
logic [31:0] instruction, pc, target;
logic format_j;
logic signed [31:0] immediate;
string trace_file;
control_immediate dut (.*);
function automatic [31:0] encode_b(input logic signed [12:0] offset);
encode_b = {offset[12], offset[10:5], 5'd0, 5'd0, 3'b000, offset[4:1], offset[11], 7'h63};
endfunction
function automatic [31:0] encode_j(input logic signed [20:0] offset);
encode_j = {offset[20], offset[10:1], offset[11], offset[19:12], 5'd1, 7'h6f};
endfunction
initial begin
if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
pc = 32'h100; format_j = 0; instruction = encode_b(13'sd12); #1;
if (immediate !== 12 || target !== 32'h10c) $fatal(1, "FAIL branch imm=%0d target=%h", immediate, target);
format_j = 1; instruction = encode_j(-21'sd8); #1;
if (immediate !== -8 || target !== 32'h0f8) $fatal(1, "FAIL jal imm=%0d target=%h", immediate, target);
$display("PASS task02 branch_imm=12 branch_target=0000010c jal_imm=-8 jal_target=000000f8");
$finish;
end
endmodule