user
24 lines
1.1 KiB
Systemverilog
24 lines
1.1 KiB
Systemverilog
module tb;
|
|
logic clk = 0, rst = 1, jump = 0, branch_taken = 0;
|
|
logic [31:0] target = 0, pc;
|
|
logic [31:0] expected [0:6] = '{32'h0,32'h4,32'h8,32'h20,32'h24,32'h10,32'h14};
|
|
string trace_file;
|
|
program_counter dut (.*);
|
|
always #1 clk = ~clk;
|
|
task automatic tick_and_check(input integer index);
|
|
@(posedge clk); #1;
|
|
if (pc !== expected[index]) $fatal(1, "FAIL index=%0d pc=%h expected=%h", index, pc, expected[index]);
|
|
endtask
|
|
initial begin
|
|
if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
|
|
tick_and_check(0); @(negedge clk); rst = 0;
|
|
tick_and_check(1); tick_and_check(2);
|
|
@(negedge clk); branch_taken = 1; target = 32'h20; tick_and_check(3);
|
|
@(negedge clk); branch_taken = 0; tick_and_check(4);
|
|
@(negedge clk); jump = 1; target = 32'h10; tick_and_check(5);
|
|
@(negedge clk); jump = 0; tick_and_check(6);
|
|
$display("PASS task03 pc=00000000,00000004,00000008,00000020,00000024,00000010,00000014 branches=1 jumps=1");
|
|
$finish;
|
|
end
|
|
endmodule
|