feat(L04): add RV32I decoder and register file card
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<svg xmlns="http://www.w3.org/2000/svg" width="600" height="210" viewBox="0 0 600 210" role="img" aria-labelledby="title desc">
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<title id="title">Ścieżka dekodowania instrukcji RV32I</title><desc id="desc">Instrukcja jest dzielona na pola, dekoder wybiera klasę, a bank rejestrów dostarcza operandy.</desc>
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<defs><marker id="a" markerWidth="9" markerHeight="9" refX="8" refY="3" orient="auto"><path d="M0 0L0 6L8 3z" fill="#16324a"/></marker></defs>
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<rect width="600" height="210" fill="#f7fafc"/>
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<g fill="#eef3f7" stroke="#16324a" stroke-width="2"><rect x="20" y="58" width="135" height="84" rx="10"/><rect x="220" y="58" width="135" height="84" rx="10"/><rect x="420" y="58" width="160" height="84" rx="10"/></g>
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<g font-family="system-ui,sans-serif" text-anchor="middle" fill="#16324a"><text x="87" y="91" font-size="18" font-weight="700">INSTR[31:0]</text><text x="87" y="118" font-size="14">opcode · rd · rs1</text><text x="287" y="91" font-size="18" font-weight="700">DEKODER</text><text x="287" y="118" font-size="14">klasa / illegal</text><text x="500" y="91" font-size="18" font-weight="700">REGISTER FILE</text><text x="500" y="118" font-size="14">x0 · rs1 · rs2 · rd</text></g>
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<g stroke="#16324a" stroke-width="3" marker-end="url(#a)"><path d="M155 100H210"/><path d="M355 100H410"/></g>
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<text x="300" y="184" font-family="system-ui,sans-serif" text-anchor="middle" font-size="15" fill="#b6402d">Nieznane kodowanie → illegal, nigdy przypadkowe sterowanie.</text>
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</svg>
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\vspace{1.0em}
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\noindent{\Large\bfseries Cel karty}\par
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\vspace{0.35em}
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Uczeń rozkłada instrukcję RV32I na pola, klasyfikuje opcode bez stanów niejawnych i dowodzi inwariantu rejestru x0.
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\vspace{0.7em}
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\noindent{\Large\bfseries Zakres tasków}\par
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\small\begin{tabularx}{\textwidth}{@{}>{\ttfamily\raggedright\arraybackslash}p{1.10cm}>{\ttfamily\raggedright\arraybackslash}p{1.45cm}X>{\raggedright\arraybackslash}p{2.50cm}>{\raggedright\arraybackslash}p{1.75cm}>{\ttfamily\raggedright\arraybackslash}p{1.50cm}@{}}
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\textbf{Krok} & \textbf{Numer tasku} & \textbf{Najważniejsza idea} & \textbf{Priorytet} & \textbf{Status} & \textbf{Version} \\ \hline
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\texttt{4} & \texttt{Task01} & pola i sign extension & obowiązkowe & opracowane & \texttt{v00.01} \\ \hline
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\texttt{4} & \texttt{Task02} & klasy opcode i illegal & obowiązkowe & opracowane & \texttt{v00.01} \\ \hline
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\texttt{5} & \texttt{Task03} & bank rejestrów i x0 & obowiązkowe & opracowane & \texttt{v00.01} \\ \hline
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\section{Task01 · Pola instrukcji}
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||||
\noindent drzewka: \pdftooltip[width=\textwidth]{D1}{RV04.WE01.OG.IP.01 | WE 01: Dekodowanie RV32I. Zaprojektowanie weryfikowalnego front-endu\textCR RV32I. | EN IP WO RV04.01: Uczeń analizuje kodowanie instrukcji. | KW IP WS RV04.01: Pola i\textCR immediate są zgodne z kodowaniem.} \pdftooltip[width=\textwidth]{D2}{RV04.WE01.TECH.I4.01 | WE 01: Dekodowanie RV32I. Zaprojektowanie weryfikowalnego front-endu\textCR RV32I. | EK INF04 RV04.01: Uczeń tworzy dekoder i bank rejestrów. | KW INF04 RV04.01:\textCR Testbenche kończą się PASS i zapisują VCD.}\par
|
||||
\vspace{0.10em}%
|
||||
\noindent K1: Zapisz pola przed uruchomieniem testu.\quad D1\par
|
||||
\ESCTinyStepSeparator
|
||||
\noindent K2: Porównaj model, RTL i VCD.\quad D2\par
|
||||
\par\vspace{0.18em}%
|
||||
\endgroup
|
||||
|
||||
Rozłóż słowo \texttt{0xFFC30293}. Pole immediate ma 12 bitów i jest rozszerzane znakiem z \texttt{instr[31]}, dlatego wynik wynosi -4.
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[width=0.9\linewidth]{\detokenize{../assets/decoder-path.png}}
|
||||
\caption{Instrukcja przechodzi przez ekstrakcję pól i dekoder do banku rejestrów.}
|
||||
\label{fig:decoder-path}
|
||||
\end{figure}
|
||||
\ESCSectionBlockEnd
|
||||
|
||||
\ESCSectionBlockStart
|
||||
\section{Task02 · Klasy opcode}
|
||||
\reversemarginpar
|
||||
\marginnote[%
|
||||
\begin{minipage}{\marginparwidth}%
|
||||
\raggedright
|
||||
{\fontsize{3.55}{3.95}\selectfont\ttfamily
|
||||
\begin{minipage}[t]{\marginparwidth}%
|
||||
\raggedright
|
||||
{\bfseries\textcolor{black!65}{TECH}\par}%
|
||||
\vspace{0.08em}%
|
||||
\hspace*{0.00em}\textcolor{red}{WE~01}\textcolor{black!48}{}\par%
|
||||
\end{minipage}%
|
||||
}%
|
||||
\end{minipage}%
|
||||
]{}[-3.1em]
|
||||
\normalmarginpar
|
||||
|
||||
\marginnote{%
|
||||
\begin{minipage}{\marginparwidth}%
|
||||
\raggedright
|
||||
{\fontsize{3.55}{3.95}\selectfont\ttfamily
|
||||
\hspace*{0.06cm}%
|
||||
\begin{minipage}[t]{\dimexpr\marginparwidth-0.06cm\relax}%
|
||||
\raggedright
|
||||
{\bfseries\textcolor{black!65}{OG}\par}%
|
||||
\vspace{0.08em}%
|
||||
\hspace*{0.00em}\textcolor{red}{WE~01}\textcolor{black!48}{}\par%
|
||||
\end{minipage}%
|
||||
}%
|
||||
\end{minipage}%
|
||||
}[-3.1em]
|
||||
|
||||
|
||||
\begingroup
|
||||
\scriptsize\ttfamily\color{black!60}\sloppy
|
||||
\noindent drzewka: \pdftooltip[width=\textwidth]{D1}{RV04.WE01.OG.IP.01 | WE 01: Dekodowanie RV32I. Zaprojektowanie weryfikowalnego front-endu\textCR RV32I. | EN IP WO RV04.01: Uczeń analizuje kodowanie instrukcji. | KW IP WS RV04.01: Pola i\textCR immediate są zgodne z kodowaniem.} \pdftooltip[width=\textwidth]{D2}{RV04.WE01.TECH.I4.01 | WE 01: Dekodowanie RV32I. Zaprojektowanie weryfikowalnego front-endu\textCR RV32I. | EK INF04 RV04.01: Uczeń tworzy dekoder i bank rejestrów. | KW INF04 RV04.01:\textCR Testbenche kończą się PASS i zapisują VCD.}\par
|
||||
\vspace{0.10em}%
|
||||
\noindent K1: Sprawdź siedem legalnych kodów i bezpieczny default.\quad D1 D2\par
|
||||
\par\vspace{0.18em}%
|
||||
\endgroup
|
||||
|
||||
Wyjścia klas są one-hot z wyjątkiem dwóch kodów skoku współdzielących sygnał jump. Domyślna gałąź ustawia illegal i nie włącza żadnej operacji.
|
||||
\ESCSectionBlockEnd
|
||||
|
||||
\ESCSectionBlockStart
|
||||
\section{Task03 · Bank rejestrów}
|
||||
\reversemarginpar
|
||||
\marginnote[%
|
||||
\begin{minipage}{\marginparwidth}%
|
||||
\raggedright
|
||||
{\fontsize{3.55}{3.95}\selectfont\ttfamily
|
||||
\begin{minipage}[t]{\marginparwidth}%
|
||||
\raggedright
|
||||
{\bfseries\textcolor{black!65}{TECH}\par}%
|
||||
\vspace{0.08em}%
|
||||
\hspace*{0.00em}\textcolor{red}{WE~01}\textcolor{black!48}{}\par%
|
||||
\end{minipage}%
|
||||
}%
|
||||
\end{minipage}%
|
||||
]{}[-3.1em]
|
||||
\normalmarginpar
|
||||
|
||||
\marginnote{%
|
||||
\begin{minipage}{\marginparwidth}%
|
||||
\raggedright
|
||||
{\fontsize{3.55}{3.95}\selectfont\ttfamily
|
||||
\hspace*{0.06cm}%
|
||||
\begin{minipage}[t]{\dimexpr\marginparwidth-0.06cm\relax}%
|
||||
\raggedright
|
||||
{\bfseries\textcolor{black!65}{OG}\par}%
|
||||
\vspace{0.08em}%
|
||||
\hspace*{0.00em}\textcolor{red}{WE~01}\textcolor{black!48}{}\par%
|
||||
\end{minipage}%
|
||||
}%
|
||||
\end{minipage}%
|
||||
}[-3.1em]
|
||||
|
||||
|
||||
\begingroup
|
||||
\scriptsize\ttfamily\color{black!60}\sloppy
|
||||
\noindent drzewka: \pdftooltip[width=\textwidth]{D1}{RV04.WE01.OG.IP.01 | WE 01: Dekodowanie RV32I. Zaprojektowanie weryfikowalnego front-endu\textCR RV32I. | EN IP WO RV04.01: Uczeń analizuje kodowanie instrukcji. | KW IP WS RV04.01: Pola i\textCR immediate są zgodne z kodowaniem.} \pdftooltip[width=\textwidth]{D2}{RV04.WE01.TECH.I4.01 | WE 01: Dekodowanie RV32I. Zaprojektowanie weryfikowalnego front-endu\textCR RV32I. | EK INF04 RV04.01: Uczeń tworzy dekoder i bank rejestrów. | KW INF04 RV04.01:\textCR Testbenche kończą się PASS i zapisują VCD.}\par
|
||||
\vspace{0.10em}%
|
||||
\noindent K1: Zapisz x5, spróbuj zapisać x0 i zmierz oba porty.\quad D1 D2\par
|
||||
\par\vspace{0.18em}%
|
||||
\endgroup
|
||||
|
||||
Dwa odczyty są kombinacyjne, zapis następuje na zboczu zegara. Adres zero omija tablicę stanu, więc x0 nie może zostać zmieniony.
|
||||
\ESCSectionBlockEnd
|
||||
|
||||
\end{document}
|
||||
@@ -0,0 +1,7 @@
|
||||
\newcommand{\PublisherDomain}{mpabi}
|
||||
\newcommand{\CardArea}{inf}
|
||||
\newcommand{\CardSeries}{rv32i-asm}
|
||||
\newcommand{\CardNumber}{04}
|
||||
\newcommand{\CardSlug}{decoder}
|
||||
\newcommand{\CardVersion}{v00.01}
|
||||
\newcommand{\DocumentUUID}{f95c41db-8abd-5623-b40d-743cc19eb469}
|
||||
Reference in New Issue
Block a user