feat(L04): add RV32I decoder and register file card

2026-07-21 16:54:03 +02:00
commit ecd7adc0ae
42 changed files with 7255 additions and 0 deletions
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+schema: 1
+card: rv32i-asm/L04
+title: The RISC-V ISA and Instruction Decoder
+steps:
+  - id: instruction-fields
+    task: task01_instruction_fields
+    action: debug
+    profile: hazard3-sim
+    target: hazard3-baremetal
+    command: stemctl debug hazard3-sim rv32i-asm L04 1
+    board:
+      show: [instruction, opcode, rd, rs1, immediate, waveform]
+      highlight: [instr-6-0, instr-11-7, instr-19-15, sign-extension]
+      question: Dlaczego immediate 0xffc oznacza -4, a nie 4092?
+    evidence: [encoding, decoded_fields, signed_immediate, trace_vcd]
+  - id: opcode-classes
+    task: task02_opcode_decoder
+    action: test
+    profile: hazard3-sim
+    target: hazard3-baremetal
+    command: stemctl test hazard3-sim rv32i-asm L04 2
+    board:
+      show: [opcode, class_outputs, illegal]
+      highlight: [one-hot-classification, default-illegal]
+      question: Które dwa opcode prowadzą do skoku?
+    evidence: [seven_legal_classes, illegal_default]
+  - id: register-file
+    task: task03_register_file
+    action: debug
+    profile: hazard3-sim
+    target: hazard3-baremetal
+    command: stemctl debug hazard3-sim rv32i-asm L04 3
+    board:
+      show: [write_port, rs1, rs2, rd1, rd2, x0, waveform]
+      highlight: [posedge-write, asynchronous-read, x0-hardwired-zero]
+      question: Co stanie się po próbie zapisu do rejestru x0?
+    evidence: [x5_write_read, x0_ignored, dual_read, trace_vcd]