feat(L04): add RV32I decoder and register file card

tests/reference_model.py

@@ -0,0 +1,35 @@
+#!/usr/bin/env python3
+import sys
+
+
+def task01() -> None:
+    instr = 0xFFC30293
+    opcode = instr & 0x7F
+    rd = (instr >> 7) & 0x1F
+    funct3 = (instr >> 12) & 0x7
+    rs1 = (instr >> 15) & 0x1F
+    imm = (instr >> 20) & 0xFFF
+    imm = imm - 0x1000 if imm & 0x800 else imm
+    assert (opcode, rd, funct3, rs1, imm) == (0x13, 5, 0, 6, -4)
+    print("PASS task01 instr=ffc30293 opcode=13 rd=5 rs1=6 funct3=0 imm=-4")
+
+
+def task02() -> None:
+    classes = {0x13: "alu_imm", 0x33: "alu_reg", 0x03: "load", 0x23: "store", 0x63: "branch", 0x6F: "jump", 0x67: "jump"}
+    assert len(classes) == 7 and 0x7F not in classes
+    print("PASS task02 legal=7 jump_opcodes=6f,67 illegal_7f=1")
+
+
+def task03() -> None:
+    regs = [0] * 32
+    regs[5] = 0x12345678
+    attempted_x0 = 0xFFFFFFFF
+    if 0 != 0:
+        regs[0] = attempted_x0
+    assert regs[5] == 0x12345678 and regs[0] == 0
+    print("PASS task03 x5=12345678 x0=00000000 dual_read=1")
+
+
+TASKS = {"task01_instruction_fields": task01, "task02_opcode_decoder": task02, "task03_register_file": task03}
+if len(sys.argv) != 2 or sys.argv[1] not in TASKS: raise SystemExit(f"usage: {sys.argv[0]} {'|'.join(TASKS)}")
+TASKS[sys.argv[1]]()