module tb;
    logic clk = 0, rst = 1, write_enable = 0;
    logic [4:0] write_address = 0, read_address1 = 0, read_address2 = 0;
    logic [31:0] write_data = 0, read_data1, read_data2;
    string trace_file;
    register_file dut (.*);
    always #1 clk = ~clk;
    initial begin
        if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
        repeat (2) @(posedge clk); @(negedge clk); rst = 0;
        write_enable = 1; write_address = 5; write_data = 32'h12345678;
        @(posedge clk); #1; write_enable = 0;
        read_address1 = 5; read_address2 = 0; #1;
        if (read_data1 != 32'h12345678 || read_data2 != 0) $fatal(1, "FAIL task03 first read");
        @(negedge clk); write_enable = 1; write_address = 0; write_data = 32'hffffffff;
        @(posedge clk); #1; write_enable = 0; read_address1 = 0; read_address2 = 5; #1;
        if (read_data1 != 0 || read_data2 != 32'h12345678) $fatal(1, "FAIL task03 x0 or dual read");
        $display("PASS task03 x5=12345678 x0=00000000 dual_read=1");
        $finish;
    end
endmodule