Files
lab-rv32i-asm-decoder/tests/task01_instruction_fields_tb.sv
T

18 lines
679 B
Systemverilog

module tb;
logic [31:0] instr;
logic [6:0] opcode, funct7;
logic [4:0] rd, rs1, rs2;
logic [2:0] funct3;
logic signed [31:0] imm_i;
string trace_file;
instruction_fields dut (.*);
initial begin
if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
instr = 32'hffc30293; #1;
if (opcode != 7'h13 || rd != 5 || rs1 != 6 || funct3 != 0 || $signed(imm_i) != -4)
$fatal(1, "FAIL task01 opcode=%h rd=%0d rs1=%0d imm=%0d", opcode, rd, rs1, $signed(imm_i));
$display("PASS task01 instr=ffc30293 opcode=13 rd=5 rs1=6 funct3=0 imm=-4");
$finish;
end
endmodule