feat(L02): add FPGA bring-up and programming card

src/tasks/task01_pin_polarity.sv

@@ -0,0 +1,3 @@
+module pin_polarity(input logic reset_n, input logic button_n, input logic led_on, output logic reset, output logic button, output logic led_n);
+  assign reset = ~reset_n; assign button = ~button_n; assign led_n = ~led_on;
+endmodule

src/tasks/task02_bringup_blinker.sv

@@ -0,0 +1,7 @@
+module bringup_blinker #(parameter integer DIVIDER=3)(input logic clk, input logic reset_n, output logic led, output logic [3:0] counter);
+  always_ff @(posedge clk) begin
+    if (!reset_n) begin counter <= 0; led <= 0; end
+    else if (counter == DIVIDER) begin counter <= 0; led <= ~led; end
+    else counter <= counter + 1'b1;
+  end
+endmodule

src/tasks/task03_programming_gate.sv

@@ -0,0 +1,13 @@
+module programming_gate(input logic clk, input logic reset, input logic cable_ok, input logic id_ok, input logic configure_ok, input logic observe_ok, output logic [2:0] state, output logic evidence_ready);
+  always_ff @(posedge clk) begin
+    if (reset) state <= 0;
+    else case (state)
+      0: if (cable_ok) state <= 1;
+      1: if (id_ok) state <= 2;
+      2: if (configure_ok) state <= 3;
+      3: if (observe_ok) state <= 4;
+      default: state <= state;
+    endcase
+  end
+  assign evidence_ready = state == 4;
+endmodule