schema: 1
card: rv32i-asm/L02
title: FPGA Bring-up and Programming
steps:
  - id: pins
    task: task01_pin_polarity
    action: test
    profile: hazard3-sim
    target: hazard3-baremetal
    command: stemctl test hazard3-sim rv32i-asm L02 1
    board: {show: [board_contract, reset_n, button_n, led_n], highlight: [active_low, explicit_pin_map, no_guessed_board], question: Które sygnały są aktywne stanem niskim?}
    evidence: [polarity, contract_status]
  - id: blinker
    task: task02_bringup_blinker
    action: debug
    profile: hazard3-sim
    target: hazard3-baremetal
    command: stemctl debug hazard3-sim rv32i-asm L02 2
    board: {show: [clock, reset_n, counter, led, trace_vcd], highlight: [known_reset, divider, edge_cycles], question: Dlaczego symulacja jest warunkiem koniecznym, ale nie dowodem działania płytki?}
    evidence: [reset_known, led_edges, trace_vcd]
  - id: physical-gate
    task: task03_programming_gate
    action: test
    profile: hazard3-sim
    target: hazard3-baremetal
    command: stemctl test hazard3-sim rv32i-asm L02 3
    board: {show: [cable, device_id, bitstream_digest, configure_log, led_observation], highlight: [ordered_gate, physical_evidence, hardware_observed_zero_in_model], question: Jakiego dowodu nadal brakuje po PASS modelu?}
    evidence: [workflow_order, preflight_claim, physical_form]