user
29 lines
1.3 KiB
YAML
29 lines
1.3 KiB
YAML
schema: 1
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card: rv32i-asm/L02
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title: FPGA Bring-up and Programming
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steps:
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- id: pins
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task: task01_pin_polarity
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action: test
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl test hazard3-sim rv32i-asm L02 1
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board: {show: [board_contract, reset_n, button_n, led_n], highlight: [active_low, explicit_pin_map, no_guessed_board], question: Które sygnały są aktywne stanem niskim?}
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evidence: [polarity, contract_status]
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- id: blinker
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task: task02_bringup_blinker
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action: debug
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl debug hazard3-sim rv32i-asm L02 2
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board: {show: [clock, reset_n, counter, led, trace_vcd], highlight: [known_reset, divider, edge_cycles], question: Dlaczego symulacja jest warunkiem koniecznym, ale nie dowodem działania płytki?}
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evidence: [reset_known, led_edges, trace_vcd]
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- id: physical-gate
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task: task03_programming_gate
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action: test
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profile: hazard3-sim
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target: hazard3-baremetal
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command: stemctl test hazard3-sim rv32i-asm L02 3
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board: {show: [cable, device_id, bitstream_digest, configure_log, led_observation], highlight: [ordered_gate, physical_evidence, hardware_observed_zero_in_model], question: Jakiego dowodu nadal brakuje po PASS modelu?}
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evidence: [workflow_order, preflight_claim, physical_form]
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