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feat(L09): add load and store semantics card

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2026-07-21 17:26:16 +02:00
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{
"$schema": "../../../../tools/card-layouts/schemas/card-source.schema.json", "schema": "esc-card-source.v1",
"card": {"id": "mpabi-inf-rv32i-asm-09-load-store", "series": "rv32i-asm", "series_title": "ASM · RV32I From Blinker to RISC-V", "number": "09", "count": "09", "slug": "load-store", "title": "L09 · Load and Store Semantics", "topic": "Maski zapisu, little-endian i sign/zero extension", "project": "Jednostka load/store RV32I", "subject": "Informatyka", "level": "Rok 1 · RTL · RV32I", "revision_date": "2026-07-21T00:00:00+02:00", "status": "Gotowa do symulacji", "version": "v00.01", "uuid": "f1efc445-93bd-5c0b-b531-52fc5a9ba943", "author": "M. Pabiszczak", "year": "2026"},
"generated": {"tex": "doc/generated/main.tex", "html": "web/index.html", "html_css": "web/style.css", "react_app": true, "html_tree_inspector": false}, "template": "templates/karta-klasyczna.json",
"title_block": {"category": "KARTA PRACY · INFORMATYKA · RTL", "standard": "ISO 7200", "prepared_by": "M. Pabiszczak", "prepared_on": "21.07.2026", "checked_by": "testy automatyczne", "approved_by": "—", "url": "http://localhost:8080", "repository_url": "https://gitea.local/edu-inf/lab-rv32i-asm-load-store", "revision": "1", "issued_on": "21.07.2026", "series": "RV32I-ASM-09", "document_type": "karta pracy", "tool": "card-layouts", "sheet": "1 / 1", "show_qr": false, "show_repository_qr": false, "height_cm": 3, "repeat_on_every_page": true, "replace_front_matter": true},
"front_page_scope": {"title": "Cel karty", "content_tex": "Uczeń implementuje linie bajtowe store, rozszerzanie load i zintegrowaną LSU z kontrolą wyrównania.", "scope_title": "Zakres tasków", "scope_table": {"headers": ["Krok", "Numer tasku", "Najważniejsza idea", "Priorytet", "Status", "Version"], "rows": [{"chapter": "11", "task": "Task01", "idea_tex": "maski SB/SH/SW", "priority": "obowiązkowe", "status": "ready", "version": "v00.01"}, {"chapter": "11", "task": "Task02", "idea_tex": "LB/LH/LW/LBU/LHU", "priority": "obowiązkowe", "status": "ready", "version": "v00.01"}, {"chapter": "11", "task": "Task03", "idea_tex": "zintegrowana LSU", "priority": "obowiązkowe", "status": "ready", "version": "v00.01"}]}},
"side_margin_tree_layout": {"columns": [{"id": "zawodowe", "label": "TECH", "side": "left", "tree": "WE -> EK -> KW", "description": "Maski store, extend load i RAM."}, {"id": "ogolne", "label": "OG", "side": "right", "tree": "WE -> EN -> KW", "description": "Analiza endian i znaku."}]},
"learning_effects": {"RV09.EN01": {"bloom_level": "Analiza", "label": "Semantyka", "text": "Uczeń analizuje little-endian, offset i sign/zero extension.", "assessment_criteria": ["RV09.KW01"]}, "RV09.EK01": {"bloom_level": "Tworzenie", "label": "LSU", "text": "Uczeń implementuje maski zapisu, wybór danych i kontrolę alignment.", "assessment_criteria": ["RV09.KW01"]}},
"assessment_criteria": {"RV09.KW01": {"text": "Maski SB/SH/SW, pary signed/unsigned load oraz modyfikacja jednej linii RAM są zgodne w modelu i RTL.", "learning_effects": ["RV09.EN01", "RV09.EK01"]}},
"educational_requirements": {"RV09.WE01": {"text": "Zbudowanie mierzalnej jednostki load/store RV32I.", "label": "Load/store", "learning_effects": ["RV09.EN01", "RV09.EK01"], "learning_tree": {"schema": "we-learning-tree.v1", "policy": "Fault zawsze zeruje write strobe.", "ogolne": [{"effect_ref": "RV09.EN01", "display": "EN IP WO RV09.01", "source": "IP", "official": "RV09.01", "local": "01", "text": "Uczeń analizuje kolejność bajtów i znak.", "kind": "WO", "tree_id": "RV09.WE01.OG.IP.01", "kw": [{"criterion_ref": "RV09.KW01", "display": "KW IP WS RV09.01", "source": "IP", "kind": "WS", "official": "RV09.01", "local": "01", "text": "Pary LB/LBU i LH/LHU mają poprawne rozszerzenie."}] }], "zawodowe": [{"effect_ref": "RV09.EK01", "display": "EK INF04 RV09.01", "source": "I4", "official": "RV09.01", "local": "01", "text": "Uczeń tworzy LSU.", "kind": "EK", "tree_id": "RV09.WE01.TECH.I4.01", "kw": [{"criterion_ref": "RV09.KW01", "display": "KW INF04 RV09.01", "source": "I4", "kind": "KW", "official": "RV09.01", "local": "01", "text": "SB zmienia wyłącznie wybraną linię, a fault chroni RAM."}] }]}}},
"sections": [
{"title": "Task01 · Linie store", "order": 10, "content_kind": "prose", "content_tex": "Utwórz strobe i przesunięte dane dla SB, SH oraz SW. Niewyrównany halfword lub word musi dać fault i maskę zero.", "educational_requirement_refs": ["RV09.WE01"], "learning_effect_refs": ["RV09.EN01", "RV09.EK01"], "assessment_criterion_refs": ["RV09.KW01"], "area_tree_refs": ["RV09.WE01.OG.IP.01", "RV09.WE01.TECH.I4.01"], "steps": [{"id": "T01-PREDICT", "title": "Przewidź maski SB +3, SH +2 i SW +0.", "tree_refs": ["RV09.WE01.OG.IP.01"], "educational_requirement_refs": ["RV09.WE01"], "learning_effect_refs": ["RV09.EN01"], "assessment_criterion_refs": ["RV09.KW01"]}, {"id": "T01-TRACE", "title": "Zmierz strobe, dane, fault i zapisz VCD.", "tree_refs": ["RV09.WE01.TECH.I4.01"], "educational_requirement_refs": ["RV09.WE01"], "learning_effect_refs": ["RV09.EK01"], "assessment_criterion_refs": ["RV09.KW01"]}], "assets": [{"path": "assets/load-store.png", "html_path": "assets/load-store.svg", "caption": "Store wybiera linie RAM, a load wybiera i rozszerza fragment słowa.", "label": "fig:load-store", "alt": "Diagram store lanes, RAM, select i extend.", "kind": "diagram", "width": 0.9}]},
{"title": "Task02 · Rozszerzanie load", "order": 20, "content_kind": "prose", "content_tex": "Wybierz bajt lub halfword zgodnie z little-endian. LB/LH replikują znak, LBU/LHU dopełniają zerami, LW zwraca słowo.", "educational_requirement_refs": ["RV09.WE01"], "learning_effect_refs": ["RV09.EN01", "RV09.EK01"], "assessment_criterion_refs": ["RV09.KW01"], "area_tree_refs": ["RV09.WE01.OG.IP.01", "RV09.WE01.TECH.I4.01"], "steps": [{"id": "T02-EXTEND", "title": "Porównaj LB/LBU dla 80 hex oraz LH/LHU dla 80ff hex.", "tree_refs": ["RV09.WE01.OG.IP.01", "RV09.WE01.TECH.I4.01"], "educational_requirement_refs": ["RV09.WE01"], "learning_effect_refs": ["RV09.EN01", "RV09.EK01"], "assessment_criterion_refs": ["RV09.KW01"]}]},
{"title": "Task03 · Zintegrowana LSU", "order": 30, "content_kind": "prose", "content_tex": "Zapisz słowo 11223344, następnie bajt aa pod offsetem 1. Odczytaj pełne słowo, LB i LBU, a na końcu wymuś niewyrównany LW.", "educational_requirement_refs": ["RV09.WE01"], "learning_effect_refs": ["RV09.EN01", "RV09.EK01"], "assessment_criterion_refs": ["RV09.KW01"], "area_tree_refs": ["RV09.WE01.OG.IP.01", "RV09.WE01.TECH.I4.01"], "steps": [{"id": "T03-LSU", "title": "Zmierz 1122aa44, ffffffaa, 000000aa i fault.", "tree_refs": ["RV09.WE01.OG.IP.01", "RV09.WE01.TECH.I4.01"], "educational_requirement_refs": ["RV09.WE01"], "learning_effect_refs": ["RV09.EN01", "RV09.EK01"], "assessment_criterion_refs": ["RV09.KW01"]}]}
],
"tasks": {"task01": {"prompt_tex": "Zweryfikuj maski i dane SB/SH/SW.", "criterion": "sb_strobe=1000 sb_data=aa000000 sh_strobe=1100 sh_data=beef0000 sw_strobe=1111 fault=1", "educational_requirement_refs": ["RV09.WE01"], "learning_effect_refs": ["RV09.EN01", "RV09.EK01"], "assessment_criterion_ref": "RV09.KW01", "links": {"equations": [], "figures": ["fig:load-store"]}}, "task02": {"prompt_tex": "Porównaj signed i unsigned load.", "criterion": "lb=ffffff80 lbu=00000080 lh=ffff80ff lhu=000080ff", "educational_requirement_refs": ["RV09.WE01"], "learning_effect_refs": ["RV09.EN01", "RV09.EK01"], "assessment_criterion_ref": "RV09.KW01", "links": {"equations": [], "figures": ["fig:load-store"]}}, "task03": {"prompt_tex": "Wykonaj sekwencję SW, SB, LW, LB i LBU.", "criterion": "word=1122aa44 lb=ffffffaa lbu=000000aa fault=1", "educational_requirement_refs": ["RV09.WE01"], "learning_effect_refs": ["RV09.EN01", "RV09.EK01"], "assessment_criterion_ref": "RV09.KW01", "links": {"equations": [], "figures": ["fig:load-store"]}}},
"tasks_order": ["task01", "task02", "task03"], "mission": "Połącz maski byte lanes, little-endian i rozszerzanie danych w kompletnej LSU.", "objectives": ["Utworzysz strobe SB/SH/SW.", "Wykonasz signed i unsigned load.", "Zweryfikujesz zintegrowaną LSU z fault."],
"agenda": [{"time": "0--25 min", "work": "Maski store."}, {"time": "25--45 min", "work": "Rozszerzanie load."}, {"time": "45--75 min", "work": "LSU, RAM i VCD."}],
"tech_stack": {"software": [{"name": "SystemVerilog", "use": "LSU i byte lanes"}, {"name": "Verilator", "use": "test i VCD"}, {"name": "stemctl", "use": "profile wykonania"}], "hardware": [{"name": "Brak wymaganego FPGA", "use": "deterministyczna symulacja RTL"}]},
"theory_refs": {"intro": "Funct3 wybiera szerokość i znak load/store, a dwa młodsze bity adresu wybierają położenie danych w słowie.", "known_refs": [], "new_concepts": [{"term": "write strobe", "definition": "Maska linii bajtowych, które wolno zmienić."}, {"term": "zero extension", "definition": "Uzupełnienie wybranej wartości zerami do 32 bitów."}]},
"container_test": {"title": "Test bez płytki", "commands": ["stemctl test native-amd64 rv32i-asm L09 1", "stemctl test hazard3-sim rv32i-asm L09 2", "stemctl debug hazard3-sim rv32i-asm L09 3"], "pass_condition": "Modele i RTL zwracają trzy komunikaty PASS, a debug zapisuje VCD."},
"safety_rules": [{"title": "Fault blokuje store", "body": "Każdy alignment fault zeruje write strobe."}, {"title": "Little-endian", "body": "Offset zero zawsze wybiera bity 7:0 słowa."}],
"hardware_procedure": [{"step": "1", "action": "Wyznacz maski store.", "condition": "Maski zapisane przed RTL."}, {"step": "2", "action": "Porównaj signed/unsigned load.", "condition": "Pary różnią się wyłącznie rozszerzeniem."}, {"step": "3", "action": "Wykonaj sekwencję LSU i zapisz VCD.", "condition": "Słowo 1122aa44, LB/LBU i fault."}], "references": []
}