schema: 1
card: rv32i-asm/L09
title: Load and Store Semantics
steps:
  - id: store-lanes
    task: task01_store_lanes
    action: debug
    profile: hazard3-sim
    target: hazard3-baremetal
    command: stemctl debug hazard3-sim rv32i-asm L09 1
    board:
      show: [address_low, funct3, store_value, write_strobe, bus_write_data, fault, waveform]
      highlight: [sb_lane_3, sh_lanes_2_3, sw_all_lanes]
      question: Dlaczego SB pod offsetem 3 tworzy maskę 1000?
    evidence: [sb_mask_data, sh_mask_data, sw_mask, rejected_misaligned, trace_vcd]
  - id: load-extend
    task: task02_load_extend
    action: test
    profile: hazard3-sim
    target: hazard3-baremetal
    command: stemctl test hazard3-sim rv32i-asm L09 2
    board:
      show: [memory_word, address_low, funct3, selected_value, read_data]
      highlight: [little_endian_lane, sign_extension, zero_extension]
      question: Dlaczego bajt 0x80 daje ffffff80 dla LB, ale 00000080 dla LBU?
    evidence: [lb_lbu_pair, lh_lhu_pair, word_load]
  - id: integrated-lsu
    task: task03_load_store_unit
    action: debug
    profile: hazard3-sim
    target: hazard3-baremetal
    command: stemctl debug hazard3-sim rv32i-asm L09 3
    board:
      show: [address, write_enable, funct3, write_strobe, memory_word, read_data, fault, waveform]
      highlight: [sw_11223344, sb_lane_1_aa, lb_lbu_readback]
      question: Które osiem bitów słowa zmieni zapis SB pod adresem 1?
    evidence: [modified_word, signed_load, unsigned_load, alignment_fault, trace_vcd]