user
19 lines
928 B
Systemverilog
19 lines
928 B
Systemverilog
module tb;
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logic [31:0] memory_word, read_data;
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logic [1:0] address_low;
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logic [2:0] funct3;
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logic fault;
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string trace_file;
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load_extend dut (.*);
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initial begin
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if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
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memory_word=32'h80ff7f01; address_low=3; funct3=0; #1; if(read_data!==32'hffffff80||fault)$fatal(1,"FAIL LB %h",read_data);
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funct3=4; #1; if(read_data!==32'h80||fault)$fatal(1,"FAIL LBU %h",read_data);
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address_low=2; funct3=1; #1; if(read_data!==32'hffff80ff||fault)$fatal(1,"FAIL LH %h",read_data);
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funct3=5; #1; if(read_data!==32'h80ff||fault)$fatal(1,"FAIL LHU %h",read_data);
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address_low=0; funct3=2; #1; if(read_data!==memory_word||fault)$fatal(1,"FAIL LW %h",read_data);
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$display("PASS task02 lb=ffffff80 lbu=00000080 lh=ffff80ff lhu=000080ff");
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$finish;
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end
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endmodule
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