user
25 lines
1.2 KiB
Systemverilog
25 lines
1.2 KiB
Systemverilog
module tb;
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logic clk=0, request=0, write_enable=0;
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logic [31:0] address=0, write_data=0, read_data;
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logic [2:0] funct3=0;
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logic fault;
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string trace_file;
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load_store_unit dut (.*);
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always #1 clk=~clk;
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task automatic store(input logic [31:0] addr, input logic [2:0] size, input logic [31:0] data);
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@(negedge clk); request=1; write_enable=1; address=addr; funct3=size; write_data=data;
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@(posedge clk); #1;
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endtask
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initial begin
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if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
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store(0,2,32'h11223344); store(1,0,32'haa);
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@(negedge clk); write_enable=0; address=0; funct3=2; #1;
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if(read_data!==32'h1122aa44||fault)$fatal(1,"FAIL word=%h",read_data);
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address=1; funct3=0; #1; if(read_data!==32'hffffffaa||fault)$fatal(1,"FAIL LB=%h",read_data);
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funct3=4; #1; if(read_data!==32'haa||fault)$fatal(1,"FAIL LBU=%h",read_data);
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address=2; funct3=2; #1; if(!fault||read_data!==0)$fatal(1,"FAIL fault=%b data=%h",fault,read_data);
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$display("PASS task03 word=1122aa44 lb=ffffffaa lbu=000000aa fault=1");
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$finish;
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end
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endmodule
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