user
22 lines
1.0 KiB
Systemverilog
22 lines
1.0 KiB
Systemverilog
module tb;
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logic [1:0] address_low;
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logic [2:0] funct3;
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logic [31:0] store_value, bus_write_data;
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logic [3:0] write_strobe;
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logic fault;
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string trace_file;
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store_lanes dut (.*);
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initial begin
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if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
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address_low=3; funct3=0; store_value=32'haa; #1;
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if (write_strobe!==4'b1000 || bus_write_data!==32'haa000000 || fault) $fatal(1,"FAIL SB");
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address_low=2; funct3=1; store_value=32'hbeef; #1;
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if (write_strobe!==4'b1100 || bus_write_data!==32'hbeef0000 || fault) $fatal(1,"FAIL SH");
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address_low=0; funct3=2; store_value=32'h12345678; #1;
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if (write_strobe!==4'b1111 || bus_write_data!==store_value || fault) $fatal(1,"FAIL SW");
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address_low=1; funct3=1; #1; if (!fault || write_strobe!==0) $fatal(1,"FAIL misaligned");
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$display("PASS task01 sb_strobe=1000 sb_data=aa000000 sh_strobe=1100 sh_data=beef0000 sw_strobe=1111 fault=1");
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$finish;
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end
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endmodule
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