user
13 lines
316 B
Systemverilog
13 lines
316 B
Systemverilog
module positional_encoding(
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input logic [7:0] value,
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output logic [7:0] bits,
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output logic [3:0] hex_high,
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output logic [3:0] hex_low,
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output logic [8:0] weighted_sum
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);
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assign bits = value;
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assign hex_high = value[7:4];
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assign hex_low = value[3:0];
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assign weighted_sum = {1'b0, value};
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endmodule
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