user
14 lines
446 B
Systemverilog
14 lines
446 B
Systemverilog
module extension_shifts(
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input logic [7:0] value,
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input logic [2:0] shift,
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output logic [31:0] zero_extended,
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output logic [31:0] sign_extended,
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output logic [31:0] logical_right,
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output logic [31:0] arithmetic_right
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);
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assign zero_extended = {24'b0, value};
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assign sign_extended = {{24{value[7]}}, value};
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assign logical_right = zero_extended >> shift;
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assign arithmetic_right = $signed(sign_extended) >>> shift;
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endmodule
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