user
24 lines
912 B
Systemverilog
24 lines
912 B
Systemverilog
module tb;
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logic [4:0] register_index;
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logic [2:0] abi_class;
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integer index, args=0, saved=0, temporaries=0, fixed=0;
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string trace_file;
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abi_registers dut (.*);
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initial begin
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if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
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for (index=0; index<32; index+=1) begin
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register_index=index[4:0]; #1;
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case (abi_class)
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3: args+=1;
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4: saved+=1;
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5: temporaries+=1;
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0,1,2,6: fixed+=1;
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default: $fatal(1, "FAIL class index=%0d class=%0d", index, abi_class);
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endcase
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end
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if (args!=8 || saved!=12 || temporaries!=7 || fixed!=5) $fatal(1, "FAIL counts %0d %0d %0d %0d", args,saved,temporaries,fixed);
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$display("PASS task02 args=8 saved=12 temporaries=7 fixed=5");
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$finish;
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end
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endmodule
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