Files
lab-rv32i-asm-subroutines-abi/tests/task03_call_stack_tb.sv
T
2026-07-21 17:19:51 +02:00

25 lines
1.2 KiB
Systemverilog

module tb;
logic clk=0, rst=1, call=0, ret=0;
logic [31:0] link=0, return_address;
logic [2:0] depth;
logic overflow, underflow;
string trace_file;
call_stack dut (.*);
always #1 clk=~clk;
task automatic action(input logic do_call, input logic do_ret, input logic [31:0] value);
@(negedge clk); call=do_call; ret=do_ret; link=value;
@(posedge clk); #1; call=0; ret=0;
endtask
initial begin
if ($value$plusargs("trace=%s", trace_file)) begin $dumpfile(trace_file); $dumpvars(0, tb); end
@(posedge clk); #1; rst=0;
action(1,0,32'h104); if (depth!==1) $fatal(1,"FAIL depth1=%0d",depth);
action(1,0,32'h204); if (depth!==2) $fatal(1,"FAIL depth2=%0d",depth);
action(0,1,0); if (return_address!==32'h204 || depth!==1) $fatal(1,"FAIL return1=%h depth=%0d",return_address,depth);
action(0,1,0); if (return_address!==32'h104 || depth!==0) $fatal(1,"FAIL return2=%h depth=%0d",return_address,depth);
action(0,1,0); if (!underflow || depth!==0) $fatal(1,"FAIL underflow=%b depth=%0d",underflow,depth);
$display("PASS task03 returns=00000204,00000104 underflow=1 max_depth=2");
$finish;
end
endmodule