feat: add lab-rv32i-c-gpio-edges-debounce card
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@@ -0,0 +1,181 @@
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#include "c13_common.h"
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#define TASK04_GPIO_INPUT (UINT32_C(1) << 4)
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#define TASK04_GPIO_EFFECT (UINT32_C(1) << 0)
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#define TASK04_UART_EFFECT (UINT32_C(1) << 1)
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#define TASK04_TIMER_EFFECT (UINT32_C(1) << 2)
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#define TASK04_TIMER_PERIOD UINT64_C(10000)
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volatile uint32_t g_task04_timer_irq_count;
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volatile uint32_t g_task04_timer_flag;
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volatile uint32_t g_task04_timer_mcause;
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volatile uint64_t g_task04_timer_deadline;
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volatile uint64_t g_task04_timer_observed;
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volatile uint32_t g_task04_uart_irq_count;
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volatile uint32_t g_task04_uart_irq_number;
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volatile uint32_t g_task04_uart_byte;
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volatile uint32_t g_task04_uart_flag;
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volatile uint32_t g_task04_gpio_irq_count;
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volatile uint32_t g_task04_gpio_irq_number;
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volatile uint32_t g_task04_gpio_level;
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volatile uint32_t g_task04_gpio_flag;
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volatile uint32_t g_task04_main_timer_actions;
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volatile uint32_t g_task04_main_uart_actions;
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volatile uint32_t g_task04_main_gpio_actions;
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volatile uint32_t g_task04_final_out;
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volatile uint32_t g_task04_final_in;
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volatile uint32_t g_task04_pass;
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void __attribute__((interrupt("machine"))) isr_machine_timer(void)
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{
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const uint64_t observed = c13_timer_read64();
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g_task04_timer_mcause = read_csr(mcause);
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g_task04_timer_observed = observed;
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g_task04_timer_deadline += TASK04_TIMER_PERIOD;
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c13_timer_set_compare(g_task04_timer_deadline);
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g_task04_timer_flag = 1u;
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g_task04_timer_irq_count = g_task04_timer_irq_count + 1u;
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}
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void task04_uart_handler(void)
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{
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g_task04_uart_irq_number = (uint32_t)h3irq_get_current_irq();
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g_task04_uart_byte = *tb_uart_reg(C13_UART_INDEX, TB_UART_DATA) & 0xffu;
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g_task04_uart_flag = 1u;
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g_task04_uart_irq_count = g_task04_uart_irq_count + 1u;
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}
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void task04_gpio_handler(void)
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{
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const uint32_t pending = tb_gpio_read(TB_GPIO_PENDING);
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g_task04_gpio_irq_number = (uint32_t)h3irq_get_current_irq();
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g_task04_gpio_level =
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(tb_gpio_read(TB_GPIO_IN) & TASK04_GPIO_INPUT) != 0u;
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tb_gpio_write(TB_GPIO_PENDING, pending);
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g_task04_gpio_flag = 1u;
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g_task04_gpio_irq_count = g_task04_gpio_irq_count + 1u;
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}
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static uint32_t take_flag(volatile uint32_t *flag)
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{
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uint32_t value;
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global_irq_enable(false);
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value = *flag;
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*flag = 0u;
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global_irq_enable(true);
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return value;
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}
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int main(void)
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{
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const uint32_t output_mask =
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TASK04_GPIO_EFFECT | TASK04_UART_EFFECT | TASK04_TIMER_EFFECT;
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global_irq_enable(false);
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timer_irq_enable(false);
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external_irq_enable(false);
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tb_uart_rx_irq_enable(C13_UART_INDEX, false);
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h3irq_enable(C13_UART_IRQ, false);
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h3irq_enable(C13_GPIO_IRQ, false);
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c13_timer_set_compare(UINT64_MAX);
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tb_gpio_write(TB_GPIO_DIR, output_mask);
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tb_gpio_write(TB_GPIO_OUT_CLR, output_mask);
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tb_gpio_write(TB_GPIO_RISE_EN, 0u);
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tb_gpio_write(TB_GPIO_FALL_EN, 0u);
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tb_gpio_write(TB_GPIO_PENDING, UINT32_MAX);
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tb_gpio_test_set_input(0u);
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h3irq_set_handler(C13_UART_IRQ, task04_uart_handler);
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h3irq_set_handler(C13_GPIO_IRQ, task04_gpio_handler);
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h3irq_set_priority(C13_UART_IRQ, 1u);
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h3irq_set_priority(C13_GPIO_IRQ, 2u);
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h3irq_enable(C13_UART_IRQ, true);
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h3irq_enable(C13_GPIO_IRQ, true);
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external_irq_enable(true);
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tb_uart_rx_irq_enable(C13_UART_INDEX, true);
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tb_gpio_write(TB_GPIO_RISE_EN, TASK04_GPIO_INPUT);
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g_task04_timer_deadline = c13_timer_read64() + TASK04_TIMER_PERIOD;
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c13_timer_set_compare(g_task04_timer_deadline);
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timer_irq_enable(true);
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global_irq_enable(true);
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/* Both writes are testbench stimuli, not production peripheral registers. */
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tb_uart_test_inject_rx(C13_UART_INDEX, (uint8_t)'U');
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tb_gpio_test_set_input(TASK04_GPIO_INPUT);
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while (g_task04_main_timer_actions == 0u ||
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g_task04_main_uart_actions == 0u ||
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g_task04_main_gpio_actions == 0u) {
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if (take_flag(&g_task04_uart_flag) != 0u) {
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if (g_task04_uart_byte == (uint32_t)'U') {
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tb_gpio_write(TB_GPIO_OUT_SET, TASK04_UART_EFFECT);
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}
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g_task04_main_uart_actions++;
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}
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if (take_flag(&g_task04_gpio_flag) != 0u) {
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if (g_task04_gpio_level != 0u) {
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tb_gpio_write(TB_GPIO_OUT_SET, TASK04_GPIO_EFFECT);
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}
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g_task04_main_gpio_actions++;
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}
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if (take_flag(&g_task04_timer_flag) != 0u) {
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tb_gpio_write(TB_GPIO_OUT_SET, TASK04_TIMER_EFFECT);
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g_task04_main_timer_actions++;
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}
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if (g_task04_main_timer_actions == 0u ||
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g_task04_main_uart_actions == 0u ||
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g_task04_main_gpio_actions == 0u) {
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__asm__ volatile("wfi" ::: "memory");
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}
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}
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global_irq_enable(false);
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timer_irq_enable(false);
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c13_timer_set_compare(UINT64_MAX);
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c13_external_disable();
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tb_gpio_write(TB_GPIO_RISE_EN, 0u);
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g_task04_final_out = tb_gpio_read(TB_GPIO_OUT) & output_mask;
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g_task04_final_in = tb_gpio_read(TB_GPIO_IN) &
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(output_mask | TASK04_GPIO_INPUT);
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g_task04_pass =
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g_task04_timer_irq_count == 1u &&
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g_task04_timer_mcause == C13_MACHINE_TIMER_CAUSE &&
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g_task04_timer_observed >= g_task04_timer_deadline - TASK04_TIMER_PERIOD &&
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g_task04_uart_irq_count == 1u &&
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g_task04_uart_irq_number == C13_UART_IRQ &&
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g_task04_uart_byte == (uint32_t)'U' &&
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g_task04_gpio_irq_count == 1u &&
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g_task04_gpio_irq_number == C13_GPIO_IRQ &&
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g_task04_gpio_level == 1u &&
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g_task04_main_timer_actions == 1u &&
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g_task04_main_uart_actions == 1u &&
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g_task04_main_gpio_actions == 1u &&
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g_task04_final_out == output_mask &&
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g_task04_final_in == (output_mask | TASK04_GPIO_INPUT);
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c13_report_u32("T04 timer_irq=", g_task04_timer_irq_count);
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c13_report_u32("T04 timer_mcause=", g_task04_timer_mcause);
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c13_report_u32("T04 uart_irq=", g_task04_uart_irq_count);
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c13_report_u32("T04 uart_number=", g_task04_uart_irq_number);
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c13_report_u32("T04 uart_byte=", g_task04_uart_byte);
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c13_report_u32("T04 gpio_irq=", g_task04_gpio_irq_count);
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c13_report_u32("T04 gpio_number=", g_task04_gpio_irq_number);
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c13_report_u32("T04 gpio_level=", g_task04_gpio_level);
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c13_report_u32("T04 main_timer=", g_task04_main_timer_actions);
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c13_report_u32("T04 main_uart=", g_task04_main_uart_actions);
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c13_report_u32("T04 main_gpio=", g_task04_main_gpio_actions);
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c13_report_u32("T04 final_out=", g_task04_final_out);
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c13_report_u32("T04 final_in=", g_task04_final_in);
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c13_report_u32("T04 pass=", g_task04_pass);
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return g_task04_pass ? 0 : 1;
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}
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