Files
lab-rv32i-c-interrupts/src/tasks/task03_pending_enable_matrix.c
T
2026-07-21 19:14:20 +02:00

63 lines
2.1 KiB
C

#include "c10_common.h"
volatile uint32_t g_task03_count;
volatile uint32_t g_task03_mcause;
volatile uint32_t g_task03_pending_asserted;
volatile uint32_t g_task03_blocked_without_msie;
volatile uint32_t g_task03_blocked_without_mie;
volatile uint32_t g_task03_delivered_with_both;
volatile uint32_t g_task03_pending_after;
volatile uint32_t g_task03_pass;
void __attribute__((interrupt("machine"))) isr_machine_softirq(void)
{
g_task03_mcause = read_csr(mcause);
tb_clr_softirq(0);
g_task03_count++;
}
int main(void)
{
c10_disable_interrupts();
tb_set_softirq(0);
c10_settle();
g_task03_pending_asserted =
(read_csr(mip) & MIP_MSIP) != 0u ? 1u : 0u;
c10_global_irq_enable(true);
c10_settle();
g_task03_blocked_without_msie = g_task03_count == 0u ? 1u : 0u;
c10_global_irq_enable(false);
c10_software_irq_enable(true);
c10_settle();
g_task03_blocked_without_mie = g_task03_count == 0u ? 1u : 0u;
c10_global_irq_enable(true);
g_task03_delivered_with_both = c10_wait_for(&g_task03_count, 1u) ? 1u : 0u;
c10_global_irq_enable(false);
c10_settle();
g_task03_pending_after =
(read_csr(mip) & MIP_MSIP) != 0u ? 1u : 0u;
c10_software_irq_enable(false);
g_task03_pass = g_task03_pending_asserted == 1u &&
g_task03_blocked_without_msie == 1u &&
g_task03_blocked_without_mie == 1u &&
g_task03_delivered_with_both == 1u &&
g_task03_count == 1u &&
g_task03_mcause == MACHINE_SOFTWARE_IRQ_CAUSE &&
g_task03_pending_after == 0u;
c10_report("T03 pending=", g_task03_pending_asserted);
c10_report("T03 blocked_no_msie=", g_task03_blocked_without_msie);
c10_report("T03 blocked_no_mie=", g_task03_blocked_without_mie);
c10_report("T03 delivered_both=", g_task03_delivered_with_both);
c10_report("T03 count=", g_task03_count);
c10_report("T03 mcause=", g_task03_mcause);
c10_report("T03 pending_after=", g_task03_pending_after);
c10_report("T03 pass=", g_task03_pass);
return g_task03_pass ? 0 : 1;
}