From ac42d43d5d973502a77e950f0a9683f9a4cd14d7 Mon Sep 17 00:00:00 2001 From: "M. Pabiszczak" <2+mpabi@noreply.zsl-gitea.mpabi.pl> Date: Tue, 21 Jul 2026 17:28:10 +0200 Subject: [PATCH] feat(rv32i-asm): register completed L03-L09 cards --- catalog/rv32i-asm.json | 14 +++---- plans/informatyka/rv32i-asm.md | 21 ++++++----- series/rv32i-asm.json | 68 ++++++++++++++++++++++++++++++++++ workspace.json | 6 ++- 4 files changed, 91 insertions(+), 18 deletions(-) create mode 100644 series/rv32i-asm.json diff --git a/catalog/rv32i-asm.json b/catalog/rv32i-asm.json index ec92335..7b5054d 100644 --- a/catalog/rv32i-asm.json +++ b/catalog/rv32i-asm.json @@ -5,12 +5,12 @@ "cards": [ {"id": "L01", "repo": "lab-rv32i-asm-number-systems", "number": "01", "title": "Number Systems and Storage", "status": "planned"}, {"id": "L02", "repo": "lab-rv32i-asm-fpga-bringup", "number": "02", "title": "FPGA Bring-up and Programming", "status": "planned"}, - {"id": "L03", "repo": "lab-rv32i-asm-blinker", "number": "03", "title": "Blinker and Synchronous Logic", "status": "planned"}, - {"id": "L04", "repo": "lab-rv32i-asm-decoder", "number": "04", "title": "The RISC-V ISA and Instruction Decoder", "status": "planned"}, - {"id": "L05", "repo": "lab-rv32i-asm-alu", "number": "05", "title": "ALU and the Verilog Assembler", "status": "planned"}, - {"id": "L06", "repo": "lab-rv32i-asm-control-flow", "number": "06", "title": "Control Flow — Jumps and Branches", "status": "planned"}, - {"id": "L07", "repo": "lab-rv32i-asm-addresses-memory", "number": "07", "title": "Addresses and Memory", "status": "planned"}, - {"id": "L08", "repo": "lab-rv32i-asm-subroutines-abi", "number": "08", "title": "Subroutines and the RISC-V ABI", "status": "planned"}, - {"id": "L09", "repo": "lab-rv32i-asm-load-store", "number": "09", "title": "Load and Store", "status": "planned"} + {"id": "L03", "repo": "lab-rv32i-asm-blinker", "number": "03", "title": "Blinker and Synchronous Logic", "status": "existing"}, + {"id": "L04", "repo": "lab-rv32i-asm-decoder", "number": "04", "title": "The RISC-V ISA and Instruction Decoder", "status": "existing"}, + {"id": "L05", "repo": "lab-rv32i-asm-alu", "number": "05", "title": "ALU and the Verilog Assembler", "status": "existing"}, + {"id": "L06", "repo": "lab-rv32i-asm-control-flow", "number": "06", "title": "Control Flow — Jumps and Branches", "status": "existing"}, + {"id": "L07", "repo": "lab-rv32i-asm-addresses-memory", "number": "07", "title": "Addresses and Memory", "status": "existing"}, + {"id": "L08", "repo": "lab-rv32i-asm-subroutines-abi", "number": "08", "title": "Subroutines and ABI", "status": "existing"}, + {"id": "L09", "repo": "lab-rv32i-asm-load-store", "number": "09", "title": "Load and Store Semantics", "status": "existing"} ] } diff --git a/plans/informatyka/rv32i-asm.md b/plans/informatyka/rv32i-asm.md index 9bdbbf3..1d92566 100644 --- a/plans/informatyka/rv32i-asm.md +++ b/plans/informatyka/rv32i-asm.md @@ -1,24 +1,25 @@ # ASM · RV32I From Blinker to RISC-V -Status: plan, 9 lekcji. +Status: L03--L09 opracowane i testowane; L01--L02 pozostają w planie. ```text ASM · RV32I From Blinker to RISC-V ├── L01 · Number Systems and Storage ├── L02 · FPGA Bring-up and Programming -├── L03 · Blinker and Synchronous Logic [steps 1–3] -├── L04 · The RISC-V ISA and Instruction Decoder [steps 4–5] -├── L05 · ALU and the Verilog Assembler [steps 6–7] -├── L06 · Control Flow — Jumps and Branches [steps 8–9] -├── L07 · Addresses and Memory [steps 10–11] -├── L08 · Subroutines and the RISC-V ABI [steps 13–14] -└── L09 · Load and Store [steps 15–16] +├── L03 · Blinker and Synchronous Logic [existing · 3 taski] +├── L04 · The RISC-V ISA and Instruction Decoder [existing · 3 taski] +├── L05 · ALU and the Verilog Assembler [existing · 3 taski] +├── L06 · Control Flow — Jumps and Branches [existing · 3 taski] +├── L07 · Addresses and Memory [existing · 3 taski] +├── L08 · Subroutines and ABI [existing · 3 taski] +└── L09 · Load and Store Semantics [existing · 3 taski] ``` L01 dostarcza języka liczb, kodowania i pamięci. L02 ustanawia fizyczną drabinkę FPGA. Kolejne karty prowadzą od logiki synchronicznej do rdzenia, -który wykonuje podstawowe instrukcje RV32I. Step 12 pozostaje późniejszym -przeglądem jakości implementacji. +który wykonuje podstawowe instrukcje RV32I. Karty L03--L09 mają niezależny +model AMD64, self-checking RTL w profilu `hazard3-sim`, artefakt VCD, widok +React oraz dwustronicowy PDF A4. Uruchomienie odbywa się przez `stemctl`. Materiał źródłowy programu: `series/inf/lab-rv32i-c-pointers-arrays/guidelines/year-01-interrupts-to-year-02-freertos.md`. diff --git a/series/rv32i-asm.json b/series/rv32i-asm.json new file mode 100644 index 0000000..31d7601 --- /dev/null +++ b/series/rv32i-asm.json @@ -0,0 +1,68 @@ +{ + "id": "rv32i-asm", + "title": "ASM · RV32I From Blinker to RISC-V", + "source_org": "edu-inf", + "answer_org": "c2025-1a-inf", + "source_remote": "r1", + "answer_remote": "r1a", + "fallback_branch": "main", + "workspace_dir": "inf", + "source_dir": "inf", + "default_card": "L03", + "cards": [ + { + "id": "L01", + "repo": "lab-rv32i-asm-number-systems", + "branch": "main", + "title": "Number Systems and Storage" + }, + { + "id": "L02", + "repo": "lab-rv32i-asm-fpga-bringup", + "branch": "main", + "title": "FPGA Bring-up and Programming" + }, + { + "id": "L03", + "repo": "lab-rv32i-asm-blinker", + "branch": "main", + "title": "Blinker and Synchronous Logic" + }, + { + "id": "L04", + "repo": "lab-rv32i-asm-decoder", + "branch": "main", + "title": "The RISC-V ISA and Instruction Decoder" + }, + { + "id": "L05", + "repo": "lab-rv32i-asm-alu", + "branch": "main", + "title": "ALU and the Verilog Assembler" + }, + { + "id": "L06", + "repo": "lab-rv32i-asm-control-flow", + "branch": "main", + "title": "Control Flow — Jumps and Branches" + }, + { + "id": "L07", + "repo": "lab-rv32i-asm-addresses-memory", + "branch": "main", + "title": "Addresses and Memory" + }, + { + "id": "L08", + "repo": "lab-rv32i-asm-subroutines-abi", + "branch": "main", + "title": "Subroutines and ABI" + }, + { + "id": "L09", + "repo": "lab-rv32i-asm-load-store", + "branch": "main", + "title": "Load and Store Semantics" + } + ] +} diff --git a/workspace.json b/workspace.json index eb7999a..dfffbf5 100644 --- a/workspace.json +++ b/workspace.json @@ -13,7 +13,7 @@ "title": "Legacy Informatyka series", "role": "series", "legacy": true, - "series": ["inf", "freertos"] + "series": ["inf", "rv32i-asm", "freertos"] }, { "id": "edu-fiz", @@ -39,6 +39,10 @@ "id": "inf", "file": "series/inf.json" }, + { + "id": "rv32i-asm", + "file": "series/rv32i-asm.json" + }, { "id": "fiz", "file": "series/fiz.json"