527 lines
18 KiB
Python
Executable File
527 lines
18 KiB
Python
Executable File
#!/usr/bin/env python3
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# Regblock generation script
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import argparse
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import re
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import sys
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import textwrap
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import yaml
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from collections import OrderedDict
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from math import log2, ceil
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# Regblock data structures and parser/loader
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class RegBlock:
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bus_types = ["apb"]
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field_properties = ["name", "b", "access", "info", "rst", "concat"]
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def __init__(self, name, w_data, w_addr, bus, info):
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self.name = name
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self.w_data = w_data
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self.w_addr = w_addr
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if bus not in self.bus_types:
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raise Exception("Unknown bus type: {}".format(bus))
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self.bus = bus
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self.info = info
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self.regs = []
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def add(self, reg):
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self.regs.append(reg)
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@staticmethod
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def load(file):
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y = yaml.load(file.read(), Loader=yaml.FullLoader)
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if "bus" not in y:
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sys.exit("Must specify bus type with \"bus: x\"")
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if "data" not in y:
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sys.exit("Must specify data width with \"data: x\"")
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if "addr" not in y:
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sys.exit("Must specify address width with \"addr: x\"")
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if "name" not in y:
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sys.exit("Must specify regblock name with \"name: x\"")
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rb = RegBlock(y["name"], y["data"], y["addr"], y["bus"], y["info"] if "info" in y else None)
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param_dict = {"W_DATA": y["data"]}
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if ("params" in y):
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param_dict = {**param_dict, **y["params"]}
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param_resolve = lambda x: x if type(x) is int else int(eval(x, {**param_dict}))
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# Expand any generate blocks (one level only)
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reglist = []
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for i, rspec in enumerate(y["regs"]):
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if "generate" not in rspec:
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reglist.append(rspec)
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continue
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yaml_lines = []
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emit = lambda x: yaml_lines.append(str(x))
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exec(rspec["generate"], {"_": emit, **param_dict}, dict())
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newregs = yaml.load("\n".join(yaml_lines), Loader=yaml.FullLoader)
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if newregs is not None:
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reglist.extend(newregs)
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# Then process the expanded reglist
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for rspec in reglist:
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reg = Register(rspec["name"], rb.w_data, rspec["info"] if "info" in rspec else None, rspec["wstb"] if "wstb" in rspec else None)
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rb.add(reg)
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for fspec in rspec["bits"]:
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for key in fspec:
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if key not in RegBlock.field_properties:
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raise Exception("'{}' is not a valid property for a field.".format(key))
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bitrange = fspec["b"]
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if type(bitrange) is int:
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bitrange = [bitrange, bitrange]
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reg.add(Field(
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fspec["name"] if "name" in fspec else "",
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param_resolve(bitrange[0]),
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param_resolve(bitrange[1]),
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fspec["access"],
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fspec["rst"] if "rst" in fspec else 0,
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fspec["info"] if "info" in fspec else None,
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fspec["concat"] if "concat" in fspec else None
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))
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return rb
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def accept(self, visitor):
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visitor.pre(self)
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for reg in self.regs:
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reg.accept(visitor)
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visitor.post(self)
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class Register:
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def __init__(self, name, width, info, wstrobe=None):
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assert(width > 0)
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self.name = name
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self.width = width
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self.info = info
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self.occupancy = [None] * width
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self.fields = OrderedDict()
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self.wstrobe = wstrobe
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def add(self, field):
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if field.lsb >= self.width or field.msb >= self.width or field.lsb < 0 or field.msb < 0:
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raise Exception("Field {} extends outside of register {}".format(field.name, self.name))
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if field.name in self.fields:
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raise Exception("{} already has a field called \"{}\"".format(self.name, field.name))
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for i in range(field.lsb, field.msb + 1):
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if self.occupancy[i] is not None:
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raise Exception("Field {} overlaps {} in register {}".format(field.name, self.occupancy[i], self.name))
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self.occupancy[i] = field.name
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self.fields[field.name] = field
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field.parent = self
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def accept(self, visitor):
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visitor.pre(self)
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for field in self.fields.values():
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field.accept(visitor)
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visitor.post(self)
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class Field:
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access_types = ["ro", "rov", "wo", "rw", "rf", "wf", "rwf", "sc", "w1c"]
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def __init__(self, name, msb, lsb, access, resetval=0, info="", concat=None, parent=None):
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if lsb > msb:
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raise Exception("Field width must be >= 0 in field {}".format(name))
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if access not in self.access_types:
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raise Exception("Unknown access type: {}. Recognised types: {}".format(access, ", ".join(self.access_types)))
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if access in ["sc", "w1c"] and msb != lsb:
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raise Exception("Field width must be 1 for access type '{}'".format(access))
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self.name = name
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self.msb = msb
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self.lsb = lsb
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self.access = access
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self.resetval = resetval
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self.info = info
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self.concat = concat
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self.parent = parent
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@property
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def width_decl(self):
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if self.msb == self.lsb:
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return ""
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else:
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return "[{}:0]".format(self.msb - self.lsb)
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@property
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def width(self):
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return self.msb - self.lsb + 1
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@property
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def fullname(self):
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if self.name == "":
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return self.parent.name
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else:
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return "{}_{}".format(self.parent.name, self.name)
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def accept(self, visitor):
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visitor.pre(self)
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# Base class for various useful lumps of functionality
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# which are applied as traversals on a regblock description tree
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class RegBlockVisitor:
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def pre(self, x):
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if type(x) is RegBlock:
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self.pre_regblock(x)
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elif type(x) is Register:
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self.pre_register(x)
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elif type(x) is Field:
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self.pre_field(x)
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else:
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raise TypeError()
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def post(self, x):
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if type(x) is RegBlock:
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self.post_regblock(x)
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elif type(x) is Register:
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self.post_register(x)
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elif type(x) is Field:
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self.post_field(x)
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else:
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raise TypeError()
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def pre_regblock(self, rb):
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raise NotImplementedError()
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def pre_register(self, r):
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raise NotImplementedError()
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def pre_field(self, f):
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raise NotImplementedError()
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def post_regblock(self, rb):
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raise NotImplementedError()
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def post_register(self, r):
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raise NotImplementedError()
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def post_field(self, f):
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raise NotImplementedError()
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# Verilog generation
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def width2str(w):
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return "[{}:0]".format(w - 1)
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def c_block_comment(lines, width=80, align="<"):
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blines = []
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blines.append("/" + (width - 1) * "*")
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line_fmt = "* {:" + align + str(width - 4) + "} *"
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for l in lines:
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blines.append(line_fmt.format(l.strip()))
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blines.append((width - 1) * "*" + "/")
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return blines
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def c_line_comment(line):
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if not hasattr(c_line_comment, "wrap"):
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c_line_comment.wrap = textwrap.TextWrapper(width=80, initial_indent="// ", subsequent_indent="// ")
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return "\n".join(c_line_comment.wrap.wrap(line.strip()))
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class Verilog:
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def __init__(self):
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self.header = []
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self.ports = []
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self.decls = []
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self.logic_comb = []
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self.logic_rst = []
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self.logic_clk = []
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def __add__(self, other):
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new = Verilog()
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new.header.extend(self.header)
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for n, s, o in zip(
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[new.ports, new.decls, new.logic_comb, new.logic_rst, new.logic_clk],
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[self.ports, self.decls, self.logic_comb, self.logic_rst, self.logic_clk],
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[other.ports, other.decls, other.logic_comb, other.logic_rst, other.logic_clk]):
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n.extend(s)
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n.extend(o)
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return new
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def __str__(self):
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strs = []
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strs.extend(self.header)
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strs.extend("\t" + s + ("" if s == "" or s.startswith("//") else ",") for s in self.ports[:-1])
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if len(self.ports) > 0:
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strs.append("\t" + self.ports[-1])
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strs.append(");")
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strs.append("")
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strs.extend(self.decls);
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strs.append("")
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strs.append("always @ (*) begin")
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strs.extend("\t" + s for s in self.logic_comb)
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strs.append("end")
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strs.append("")
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strs.append("always @ (posedge clk or negedge rst_n) begin")
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strs.append("\tif (!rst_n) begin")
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strs.extend("\t\t" + s for s in self.logic_rst)
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strs.append("\tend else begin")
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strs.extend("\t\t" + s for s in self.logic_clk)
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strs.append("\tend")
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strs.append("end")
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strs.append("")
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strs.append("endmodule\n")
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return "\n".join(strs)
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class VerilogWriter(RegBlockVisitor):
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def __init__(self):
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self.v = Verilog()
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self.regname = None
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self.concat = OrderedDict()
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self.wstrobe = OrderedDict()
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def pre_regblock(self, rb):
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v = self.v
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v.header.extend(c_block_comment(["AUTOGENERATED BY REGBLOCK", "Do not edit manually.",
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"Edit the source file (or regblock utility) and regenerate."], align = "^"))
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v.header.append("")
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v.header.append(c_line_comment("{:<20} : {}".format("Block name", rb.name)))
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v.header.append(c_line_comment("{:<20} : {}".format("Bus type", rb.bus)))
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v.header.append(c_line_comment("{:<20} : {}".format("Bus data width", rb.w_data)))
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v.header.append(c_line_comment("{:<20} : {}".format("Bus address width", rb.w_addr)))
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v.header.append("")
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if rb.info is not None:
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v.header.append(c_line_comment(rb.info))
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v.header.append("")
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v.header.append("module {}_regs (".format(rb.name))
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v.ports.extend(["input wire clk", "input wire rst_n",])
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addr_mask = (1 << 2 + ceil(log2(len(rb.regs)))) - 1
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addr_mask = addr_mask & (-1 << ceil(log2(rb.w_data / 8)))
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if rb.bus == "apb":
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v.ports.append("")
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v.ports.append("// APB Port")
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v.ports.append("input wire apbs_psel")
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v.ports.append("input wire apbs_penable")
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v.ports.append("input wire apbs_pwrite")
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v.ports.append("input wire {} apbs_paddr".format(width2str(rb.w_addr)))
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v.ports.append("input wire {} apbs_pwdata".format(width2str(rb.w_data)))
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v.ports.append("output wire {} apbs_prdata".format(width2str(rb.w_data)))
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v.ports.append("output wire apbs_pready")
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v.ports.append("output wire apbs_pslverr")
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v.decls.append("// APB adapter")
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v.decls.append("wire {} wdata = apbs_pwdata;".format(width2str(rb.w_data)))
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v.decls.append("reg {} rdata;".format(width2str(rb.w_data)))
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v.decls.append("wire wen = apbs_psel && apbs_penable && apbs_pwrite;")
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v.decls.append("wire ren = apbs_psel && apbs_penable && !apbs_pwrite;")
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v.decls.append("wire {} addr = apbs_paddr & {}'h{:x};".format(width2str(rb.w_addr), rb.w_addr, addr_mask))
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v.decls.append("assign apbs_prdata = rdata;")
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v.decls.append("assign apbs_pready = 1'b1;")
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v.decls.append("assign apbs_pslverr = 1'b0;")
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v.decls.append("")
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v.ports.append("")
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v.ports.append("// Register interfaces")
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for i, reg in enumerate(rb.regs):
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v.decls.append("localparam ADDR_{} = {};".format(reg.name.upper(), i * 4))
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v.decls.append("")
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for reg in rb.regs:
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v.decls.append("wire __{}_wen = wen && addr == ADDR_{};".format(reg.name, reg.name.upper()))
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v.decls.append("wire __{}_ren = ren && addr == ADDR_{};".format(reg.name, reg.name.upper()))
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v.logic_comb.append("case (addr)")
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for reg in rb.regs:
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v.logic_comb.append("\tADDR_{}: rdata = __{}_rdata;".format(reg.name.upper(), reg.name))
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v.logic_comb.append("\tdefault: rdata = {}'h0;".format(rb.w_data))
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v.logic_comb.append("endcase")
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def post_regblock(self, rb):
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for name, conns in self.concat.items():
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concat_name = "concat_{}_o".format(name)
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width = sum(f[0] for f in conns)
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self.v.ports.append("output wire [{}:0] {}".format(width - 1, concat_name))
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self.v.decls.append("assign {} = {{{}}};".format(concat_name, ", ".join(f[1] for f in reversed(conns))))
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max_strobe_index = OrderedDict()
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for name, conns in self.wstrobe.items():
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self.v.logic_rst.append("wstrobe_{} <= 1'b0;".format(name))
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self.v.logic_clk.append("wstrobe_{} <= {};".format(name, " || ".join(
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"__{}_wen".format(conn) for conn in conns)))
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if name.endswith("]"):
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shortname = name.split("[")[0]
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idx = int(name.split("[")[-1][:-1])
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if shortname in max_strobe_index:
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max_strobe_index[shortname] = max(max_strobe_index[shortname], idx)
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else:
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max_strobe_index[shortname] = idx
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else:
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self.v.ports.append("output reg wstrobe_{}".format(name))
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for name, max_idx in max_strobe_index.items():
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self.v.ports.append("output reg [{}:0] wstrobe_{}".format(max_idx, name))
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def pre_register(self, reg):
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v = self.v
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self.regname = reg.name
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v.decls.append("")
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rdata_conns = []
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empty_count = 0
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last_occupant = None
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for occupant in reversed(reg.occupancy):
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if occupant is None:
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empty_count += 1
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elif occupant != last_occupant:
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if empty_count > 0:
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rdata_conns.append("{}'h0".format(empty_count))
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empty_count = 0
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rdata_conns.append("{}_rdata".format(reg.fields[occupant].fullname))
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last_occupant = occupant
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if empty_count > 0:
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rdata_conns.append("{}'h0".format(empty_count))
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for field in reg.fields.values():
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lsb = reg.occupancy.index(field.name)
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msb = lsb - 1 + reg.occupancy.count(field.name)
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index = "[{}]".format(lsb) if msb == lsb else "[{}:{}]".format(msb, lsb)
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v.decls.append("wire {} {}_wdata = wdata{};".format(field.width_decl, field.fullname, index))
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v.decls.append("wire {} {}_rdata;".format(field.width_decl, field.fullname))
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v.decls.append("wire {} __{}_rdata = {{{}}};".format(width2str(reg.width), reg.name, ", ".join(rdata_conns)))
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if reg.wstrobe is not None:
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if not reg.wstrobe in self.wstrobe:
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self.wstrobe[reg.wstrobe] = []
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self.wstrobe[reg.wstrobe].append(reg.name)
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def post_register(self, reg):
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pass
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def pre_field(self, f):
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v = self.v
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rname = self.regname
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fname = f.fullname
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if f.access in ["rov", "rf", "rwf", "w1c"]:
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v.ports.append("input wire {} {}_i".format(f.width_decl, fname))
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if f.access in ["rov", "rf", "rwf"]:
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v.decls.append("assign {}_rdata = {}_i;".format(fname, fname))
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if f.access in ["wo", "rw", "wf", "rwf", "sc", "w1c"]:
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v.ports.append("output reg {} {}_o".format(f.width_decl, fname))
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if f.access in ["wf", "rwf"]:
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v.ports.append("output reg {}_wen".format(fname))
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v.logic_comb.append("{}_wen = __{}_wen;".format(fname, rname))
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v.logic_comb.append("{}_o = {}_wdata;".format(fname, fname))
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if f.access in ["rf", "rwf"]:
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v.ports.append("output reg {}_ren".format(fname))
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v.logic_comb.append("{}_ren = __{}_ren;".format(fname, rname))
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if f.access in ["rw"]:
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v.decls.append("assign {}_rdata = {}_o;".format(fname, fname))
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if f.access in ["rw", "wo"]:
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v.logic_rst.append("{}_o <= {}'h{:x};".format(fname, f.width, f.resetval))
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v.logic_clk.append("if (__{}_wen)".format(rname))
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v.logic_clk.append("\t{}_o <= {}_wdata;".format(fname, fname))
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if f.access in ["w1c"]:
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v.logic_rst.append("{} <= {}'h{:x};".format(fname, f.width, f.resetval))
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v.decls.append("reg {} {};".format(f.width_decl, fname))
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v.decls.append("assign {}_rdata = {};".format(fname, fname))
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v.logic_clk.append("{0} <= ({0} && !(__{1}_wen && {0}_wdata)) || {0}_i;".format(fname, rname))
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v.logic_comb.append("{0}_o = {0};".format(fname))
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if f.access in ["sc"]:
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v.logic_comb.append("{0}_o = {0}_wdata & {{{1}{{__{2}_wen}}}};".format(fname, f.width, rname))
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if f.access in ["ro", "wo", "wf", "sc"]:
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v.decls.append("assign {}_rdata = {}'h{:x};".format(fname, f.width, f.resetval))
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if f.concat is not None:
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if not f.access in ["wo", "rw", "wf", "rwf", "sc"]:
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raise Exception("concat specified for port with no regblock output")
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if not f.concat in self.concat:
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self.concat[f.concat] = []
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self.concat[f.concat].append((f.width, "{}_o".format(fname)))
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# C header generation
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class HeaderWriter(RegBlockVisitor):
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def __init__(self):
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self.lines = []
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self.blockname = None
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self.regname = None
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def __str__(self):
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return "".join(l + "\n" for l in self.lines)
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def pre_regblock(self, rb):
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lines = self.lines
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self.blockname = rb.name
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lines.extend(c_block_comment(["AUTOGENERATED BY REGBLOCK", "Do not edit manually.",
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"Edit the source file (or regblock utility) and regenerate."], align = "^"))
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lines.append("")
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lines.append("#ifndef _{}_REGS_H_".format(rb.name.upper()))
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lines.append("#define _{}_REGS_H_".format(rb.name.upper()))
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lines.append("")
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lines.append(c_line_comment("{:<20} : {}".format("Block name", rb.name)))
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lines.append(c_line_comment("{:<20} : {}".format("Bus type", rb.bus)))
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lines.append(c_line_comment("{:<20} : {}".format("Bus data width", rb.w_data)))
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lines.append(c_line_comment("{:<20} : {}".format("Bus address width", rb.w_addr)))
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lines.append("")
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if rb.info is not None:
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lines.append(c_line_comment(rb.info))
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lines.append("")
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for i, reg in enumerate(rb.regs):
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lines.append("#define {}_{}_OFFS {}".format(rb.name.upper(), reg.name.upper(), i * 4))
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def post_regblock(self, rb):
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self.lines.append("")
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self.lines.append("#endif // _{}_REGS_H_".format(rb.name.upper()))
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def pre_register(self, reg):
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lines = self.lines
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lines.append("")
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lines.extend(c_block_comment([reg.name.upper()], align = "^"))
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lines.append("")
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if reg.info is not None:
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lines.append(c_line_comment(reg.info))
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lines.append("")
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self.regname = reg.name
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|
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def post_register(self, reg):
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pass
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def pre_field(self, f):
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fname = f.fullname.upper()
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lines = self.lines
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lines.append(c_line_comment("Field: {} Access: {}".format(fname, f.access.upper())))
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fname = self.blockname.upper() + "_" + fname
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if f.info is not None:
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lines.append(c_line_comment(f.info))
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lines.append("#define {}_LSB {}".format(fname, f.lsb))
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lines.append("#define {}_BITS {}".format(fname, f.width))
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mask = 0
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for i in range(32):
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if i in range(f.lsb, f.msb + 1):
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mask = mask | (1 << i)
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lines.append("#define {}_MASK {:#x}".format(fname, mask))
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|
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def change_ext(fname, ext):
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return ".".join(fname.split(".")[0:-1] + [ext.strip(".")])
|
|
|
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if __name__ == "__main__":
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parser = argparse.ArgumentParser()
|
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parser.add_argument("src", help="Source file to read from (pass - for stdin)")
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parser.add_argument("--verilog", "-v", help="Verilog file to write to (pass - for stdout)")
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parser.add_argument("--cheader", "-c", help="C header file to write to (pass - for stdout)")
|
|
parser.add_argument("--all", "-a", action="store_true", help="Generate all output types, with default filenames")
|
|
args = parser.parse_args()
|
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sfile = None
|
|
vfile = None
|
|
hfile = None
|
|
if args.src == "-" and args.all:
|
|
exit("Cannot use --all with stdin input")
|
|
if args.src == "-":
|
|
sfile = sys.stdin
|
|
else:
|
|
sfile = open(args.src)
|
|
rb = RegBlock.load(sfile)
|
|
|
|
if args.verilog is not None or args.all:
|
|
if args.verilog == "-":
|
|
vfile = sys.stdout
|
|
elif args.verilog is None:
|
|
vfile = open(change_ext(args.src, ".v"), "w")
|
|
else:
|
|
vfile = open(args.verilog, "w")
|
|
if args.cheader is not None or args.all:
|
|
if (args.cheader == "-"):
|
|
hfile = sys.stdout
|
|
elif args.verilog is None:
|
|
hfile = open(change_ext(args.src, ".h"), "w")
|
|
else:
|
|
hfile = open(args.cheader, "w")
|
|
|
|
if vfile is not None:
|
|
vw = VerilogWriter()
|
|
rb.accept(vw)
|
|
vfile.write(str(vw.v))
|
|
if hfile is not None:
|
|
hw = HeaderWriter()
|
|
rb.accept(hw)
|
|
hfile.write(str(hw))
|