feat: add lab-rv32i-freertos-event-group card
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# K13 — EventGroup and coordinated state
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## Position
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- Series: FreeRTOS C++
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- Lesson: L12, card K13
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- Duration: 30 minutes
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- Typed bits: UART=0x1, GPIO=0x2, APP=0x4
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- Static control block; no heap delta
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## Outcome
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The student designs a typed readiness mask, distinguishes any/all and
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keep/clear-on-exit, explains timeout snapshots, and rejects the interpretation
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of an event bit as a counter or payload.
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## Lesson plan
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| Time | Mode | Evidence |
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| --- | --- | --- |
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| 0–5 | typed masks | enum bits combine to all=0x7 |
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| 5–10 | publishers | coordinator Blocked; workers set 1,2,4 |
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| 10–15 | wait all | snapshot/current=0x7, satisfied |
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| 15–20 | clear one | clear GPIO returns 0x7, current=0x5 |
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| 20–25 | timeout | all unsatisfied for 3 ticks, snapshot=0x5 |
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| 25–30 | any + clear | snapshot=0x5, final=0; discuss races/counters |
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## Acceptance
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- type is an enum and masks remain typed at the wrapper boundary;
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- event-group handle equals caller static control and heap delta is zero;
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- coordinator is eBlocked before the first worker publishes;
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- repeated UART set is idempotent at mask 1;
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- all/keep gives 7 and explicit GPIO clear gives 5;
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- second all wait times out after at least 3 ticks with snapshot 5;
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- any/clear-on-exit succeeds with snapshot 5 and final mask 0;
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- target exits with PASS.
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## Main traps
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1. A bit is state, not an event count.
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2. A bit mask is not a payload record.
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3. Clear-on-exit affects all selected bits and can race with other waiters.
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4. Timeout return is a snapshot; test satisfaction explicitly.
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5. EventGroup FromISR set is deferred through the timer service task.
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